MT312 Zarlink Semiconductor, MT312 Datasheet - Page 39

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

7.0
7.1
7.1.1
bit-15:
bit-14:
Known symbol rate mode:
bits13-0:
If either of the two DSS bits are set in the CONFIG register, then the SYM_RATE register contents are ignored and
the symbol rate is taken as 20 MS/s. Hence it is not necessary to program the SYM_RATE register for DSS
applications.
Search Mode:
bits 13-12: don’t care
bits 11-0:
The total symbol rate range is divided into 12 sub-ranges. A bit in the above register pair is assigned to each
sub-range, as defined in Figure 3 below. The symbol rate sub-range or sub-ranges to be searched are defined by
setting the appropriate bits high. Small overlaps are automatically provided between successive sub-ranges. Note
that the lowest sub-ranges have been provided for 90 MHz operation and the device has not been optimised for
operation below 1 MS/s.
Therefore for example, (with a 90MHz system clock) to search for all signals with symbol rates from 15 MS/s to
45 MS/s, bits 15, 11, 10 & 9 are all set to ‘1’ and all other to ‘0’.
SYM_RATE_H
SYM_RATE_L
NAME
QPSK Demodulator Read/Write Registers
QPSK demodulator
Symbol rate registers 23 - 24 (R/W)
SR_FMT
Required symbol rate in MS/s x 256. Unsigned 14-bit number. e.g. for a symbol rate of 27.5 MS/s:
sub-ranges to be searched (scaled by clock rate).
SEARCH
SYM_RATE = 27.5 * 256 = 7040 = 1B80 (hex)
ADR
23
24
SEARCH
bit-7
bit 15 = 0
bit 15 = 1
bit 14 = 0
bit 14 = 1
SR_FMT
bit-6
SYM_RATE[7:0] in MS/s (low byte)
Zarlink Semiconductor Inc.
known symbol rate mode
search mode
normal mode, bits 13:0 = symbol rate * 256
reserved mode
bit-5
MT312
SYM_RATE[13:8] in MS/s (high byte)
39
bit-4
bit-3
bit-2
bit-1
bit-0
Design Manual
R/W
R/W
Def hex
1B
80