MT312 Zarlink Semiconductor, MT312 Datasheet - Page 54

• Manufacturer Part Number: MT312
• Description: Satellite Channel Decoder
• Manufacturer: Zarlink Semiconductor

9.0
9.1
9.1.1
bit-7:
bit-6:
bit-5-4:
AGC control output is a pulse density modulated output created by a sigma-delta modulator. To reduce power
consumption this is not clocked at the full system clock rate. The frequency at which this is clocked is the system
clock divided by the decimation factor in Table 6.
bit-3-1:
bit-0:
9.1.2
AGC_REF[7:0]
The AGC loop control in MT312 is designed to bring the mean square value of the I signal (or the Q signal) at the
ADC output (prior to any digital filtering) to the value set by the AGC_REF register.
AGC_CTRL
AGC_REF
NAME
NAME
Automatic gain control read/write registers
Automatic Gain Control
AGC control register 39 (R/W)
AGC_REF Reference Value register 41 (R/W)
AGC_SD[1:0]
AGC_BW[2:0]
AGC_SL Analogue AGC slope
Reserved.
Reserved.
High = positive slope i.e. RF gain proportional to AGC voltage.
Low = negative slope i.e. RF gain inversely proportional to AGC voltage (default).
ADR
39
ADR
41
Table 6 - Sigma Delta Clock Decimation Ratio Programming
Reserved
bit-7
bit-7
Must be set low.
Must be set low.
Sigma-Delta clock decimation ratio related to system clock.
Front End AGC bandwidth (retain default value of 3).
Front End AGC reference value.
Reserved
bit-6
bit-6
AGC_SD[1:0]
AGC_REF[7:0] AGC reference level
Zarlink Semiconductor Inc.
bit-5
00
01
10
11
AGC_SD[1:0]
bit-5
MT312
bit-4
54
bit-4
Decimation
bit-3
16
2
4
8
AGC_BW[2:0]
bit-3
bit-2
bit-2
bit-1
bit-1
bit-0
AGC_SL
bit-0
Design Manual
R/W
R/W
hex
Def
67
hex
Def
26