ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 211

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Figure 8–23. High-Speed I/O Timing Diagram
Altera Corporation-Preliminary
March 2007
Note to
(1)
Transmitter channel-to-channel skew
Sampling window
Receiver input skew margin
Input jitter tolerance (peak-to-peak)
Output jitter (peak-to-peak)
Table 8–3. High-Speed I/O Timing Definitions
The
within the LAB adjacent to the output pins.
Table
TCCS
Internal Clock
8–3:
Input Clock
Input Data
Parameter
Receiver
External
specification applies to the entire bank of differential I/O as long as the SERDES logic is placed
Table 8–3
Figure
budget.
TCCS
(1)
8–23.
defines the parameters of the timing diagram shown in
RSKM
TCCS
SW
RSKM
Symbol
Figure 8–24
Sampling Window (SW)
Time Unit Interval (TUI)
The timing difference between the fastest and slowest
output edges, including
The clock is included in the
The period of time during which the data must be valid
in order for you to capture it correctly. The setup and
hold times determine the ideal strobe position within the
sampling window. T
RSKM
for the sampling window and
is: RSKM = (TUI – SW – TCCS) / 2.
Allowed input jitter on the input clock to the PLL that is
tolerable while maintaining PLL lock.
Peak-to-peak output jitter from the PLL.
shows the Cyclone III high-speed I/O timing
is defined by the total margin left after accounting
High-Speed I/O Timing in Cyclone III Devices
Cyclone III Device Handbook, Volume 1
SW
Description
=T
RSKM
t
SU
CO
+T
TCCS
variation and clock skew.
TCCS
hd
+PLL jitter.
TCCS
. The
measurement.
RSKM
equation
8–21