ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 386

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone III Devices
Figure 14–7. Selecting the Instruction Mode
14–12
Cyclone III Device Handbook, Volume 1
TAP_STATE
TMS
TDO
TCK
TEST_LOGIC/RESET
TDI
RUN_TEST/IDLE SELECT_IR_SCAN
SELECT_DR_SCAN
The TDO pin is tri-stated in all states except in the SHIFT_IR and
SHIFT_DR states. The TDO pin is activated at the first falling edge of TCK
after entering either of the shift states and is tri-stated at the first falling
edge of TCK after leaving either of the shift states.
When the SHIFT_IR state is activated, TDO is no longer tri-stated, and the
initial state of the instruction register is shifted out on the falling edge of
TCK. The first 10 bits shifted out from the instruction register are
1010101010. TDO continues to shift out the contents of the instruction
register as long as the SHIFT_IR state is active. The TAP controller
remains in the SHIFT_IR state as long as TMS remains low.
During the SHIFT_IR state, an instruction code is entered by shifting
data on the TDI pin on the rising edge of TCK. The last bit of the
instruction code is clocked at the same time that the next state,
EXIT1_IR, is activated. Set TMS to high to activate the EXIT1_IR state.
Once in the EXIT1_IR state, TDO becomes tri-stated again. After an
instruction code is entered correctly, the TAP controller advances to
serially shift test data in one of three modes. The three serial shift test data
instruction modes are:
■
■
■
These three modes will be discussed in greater detail in the following
three sections.
SAMPLE/PRELOAD Instruction Mode
EXTEST Instruction Mode
BYPASS Instruction Mode
CAPTURE_IR
SHIFT_IR
Altera Corporation-Preliminary
EXIT1_IR
March 2007