ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 25

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Altera Corporation-Preliminary
March 2007
Note to
(1)
Single-Ended I/O
Differential I/O
Table 1–6. Cyclone III FPGA I/O Standards Support
PCI Express and Serial Rapid I/O can be supported using an external PHY device.
Table
1–6:
Type
f
I/O Features
All Cyclone III devices contain eight I/O banks. All I/O banks support
the single-ended and differential I/O standards listed in
The Cyclone III device I/O also supports programmable bus hold,
programmable pull-up and pull-down resistors, programmable slew rate
control to optimize signal integrity, and hot socketing. Cyclone III devices
support calibrated on-chip series termination (OCT) or driver impedance
matching (Rs) for single-ended I/O standards with one OCT calibration
block per side.
For more information, refer to the Device I/O Features chapter in the
Cyclone III Device Handbook.
Clock Networks and PLLs
Cyclone III FPGAs include up to 20 global clock networks. Global clock
signals can be driven from dedicated clock pins, dual purpose clock pins,
user logic, and phase-locked loops. Cyclone III FPGAs include up to four
PLLs with five outputs per PLL to provide robust clock management and
synthesis. PLLs can be used for device clock management, external
system clock management, and I/O interfaces.
Cyclone III PLLs can be dynamically reconfigured to enable
auto-calibration of external memory interfaces while the device is in
operation. This feature also enables support of multiple input source
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LVTTL
LVCMOS
SSTL
HSTL
PCI
PCI-X
SSTL
HSTL
LVPECL
LVDS
mini-LVDS
RSDS
PPDS
Note (1)
I/O Standard
Cyclone III Device Handbook, Volume 1
Cyclone III Device Architecture
Table
1–6.
1–9