ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 65

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Figure 4–8. Cyclone III Single-Port Mode Timing Waveforms
Altera Corporation-Preliminary
March 2007
q_a (new data)
q_a (old data)
address_a
wren_a
data_a
rden_a
clk_a
to either “New Data” or “Old Data” in the RAM MegaWizard in the
Quartus II software. See
for more information about read-during-write mode.
The port width configurations for M9K blocks in single-port mode are as
follows:
■
■
■
■
■
■
■
■
■
Figure 4–8
single-port mode with unregistered outputs. Registering the RAM's
outputs would simply delay the q output by one clock cycle.
A
8192 × 1
4096 × 2
2048 × 4
1024 × 8
1024 × 9
512 × 16
512 × 18
256 × 32
256 × 36
a0(old data)
A
shows timing waveforms for read and write operations in
a0
B
B
A
C
“Read-During-Write Operations” on page 4–28
C
B
D
a1(old data)
Cyclone III Device Handbook, Volume 1
D
a1
E
E
D
F
Memory Modes
E
F
4–11