ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 312

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Configuring Cyclone III Devices
Figure 10–25. JTAG Configuration of Multiple Devices Using a Download Cable
Notes to
(1)
(2)
(3)
(4)
(5)
10–76
Cyclone III Device Handbook, Volume 1
USB-Blaster, ByteBlaster II,
Pin 1
10-Pin Male Header
or ByteBlasterMV
The pull-up resistor should be connected to the same supply voltage as the USB-Blaster, MasterBlaster (V
ByteBlaster II or ByteBlasterMV cable.
Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If only JTAG
configuration is used, connect the nCONFIG pin to V
and DATA[0] to either high or low, whichever is convenient on your board.
Pin 6 of the header is a V
V
cable, this pin is a no connect. In the USB-Blaster and ByteBlaster II cable, this pin is connected to nCE when it is
used for AS programming, otherwise it is a no connect.
nCE must be connected to ground or driven low for successful JTAG configuration.
Power up the ByteBlaster II, USB Blaster, or ByteBlasterMV cable’s V
programmers must switch to 2.5 V. Pin 4 of the header is a V
MasterBlaster cable can receive power from either 5.0- or 3.3-V circuit boards, DC power supply, or 5.0 V from the
USB cable. Refer to the MasterBlaster Serial/USB Communications Data Sheet for this value.
MasterBlaster,
CCA
Figure
. Refer to the MasterBlaster Serial/USB Communications Cable Data Sheet for this value. In the ByteBlasterMV
V
CCA
(5)
1 kΩ
VIO
(3)
10 kΩ
10–25:
V
CCA
V
CCA
1 kΩ
(2)
(2)
(2)
(2)
(2)
V
CCIO
10kΩ
IO
(1)
DATA[0]
DCLK
MSEL[3..0]
TDI
nST A TUS
nCONFIG
nCEO
nCE (4)
reference voltage for the MasterBlaster output driver. V
1
1
The nCE pin must be connected to GND or driven low during JTAG
configuration. In multi-device AS, AP, PS, and FPP configuration chains,
the first device’s nCE pin is connected to GND while its nCEO pin is
connected to the nCE pin of the next device in the chain. The last device’s
TMS
Cyclone III FPGA
TCK
CONF_DONE
Power up the ByteBlaster II or USB Blaster cable’s V
2.5V supply from V
to 2.5V.
All I/O inputs must maintain a maximum AC voltage of 4.1V. If
a non-Cyclone III device is cascaded in the JTAG-chain, TDO of
the non-Cyclone III device driving into TDI of Cyclone III has to
fit the maximum overshoot equation outlined in
and JTAG Pin I/O Requirements” on page
TDO
V
CCIO
10kΩ
(1)
(2)
(2)
(2)
(2)
(2)
V
CC
CCIO
, and the MSEL[3..0] pins to ground. In addition, pull DCLK
10kΩ
(1)
nST A TUS
DATA[0]
DCLK
nCONFIG
MSEL[3..0]
nCEO
nCE (4)
TDI
TMS
Cyclone III FPGA
CC
CCA
TCK
CONF_DONE
power supply for the MasterBlaster cable. The
. Third-party programmers must switch
CC
TDO
V
with a 2.5V supply from V
CCIO
10kΩ
(1)
Altera Corporation-Preliminary
(2)
(2)
(2)
(2)
(2)
V
CCIO
IO
10kΩ
(1)
DATA[0]
DCLK
MSEL[3..0]
nCE (4)
TDI
nST A TUS
nCONFIG
nCEO
should match the device’s
TMS
Cyclone III FPGA
10–13.
CONF_DONE
TCK
“Configuration
TDO
CCA
V
CC
CCIO
. Third-party
March 2007
10kΩ
(1)
with a
IO
pin),