ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 440

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Switching Characteristics
1–30
Cyclone III Handbook
Note to
(1)
Note to
(1)
Notes to
(1)
(2)
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
t
Output Duty Cycle
OUTFULLJITTER
Table 1–37. Transmitter Channel-to-Channel Skew (TCCS) - Write Side
Table 1–38. DDIO Outputs Half-Period Jitter
Table 1–39. Duty Cycle Distortion on Cyclone III I/O Pins
Standards
Memory
Column I/Os refer to Top and Bottom I/Os. Row I/Os refer to Right and Left I/Os.
Pending silicon characterization.
Preliminary DCD specification applies to clock outputs from PLLs, global clock tree and IOE driving dedicated
and general purpose I/O pins.
Detailed DCD specification pending silicon characterization.
Name
Table
Table
Table
1–37:
1–38:
Symbol
1–39:
Lead
Column I/Os
585
610
670
Half-period jitter (PLL driving DDIO outputs)
–6 Speed Grade
Lag
585
610
670
DCD Specifications
Table 1–39
devices. Detailed information on duty cycle distortion will be published
after characterization.
Lead
645
670
725
Row I/Os
-6 Speed Grade
Min
45
lists the worst case duty cycle distortion for Cyclone III
Lag
645
670
725
Description
Max
Lead
Column I/Os
55
595
620
675
–7 Speed Grade
-7 Speed Grade
Lag
595
620
675
(1) (2)
Min
45
Lead
650
680
735
Row I/Os
Max
55
(1)
Lag
650
680
735
-8 Speed Grade
Altera Corporation- Preliminary
Min
40
Lead
Column I/Os
595
630
685
Max
–8 Speed Grade
60
Lag
595
630
685
Max
(1)
Lead
660
685
740
March 2007
Row I/Os
Unit
%
Unit
ps
Preliminary
Lag
660
685
740
Units
ps
ps
ps