ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 6

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Contents
Chapter 3. MultiTrack Interconnect in Cyclone III Devices
Chapter 4. Memory Blocks in Cyclone III Devices
vi
LE Operating Modes ............................................................................................................................. 2–5
Logic Array Blocks ................................................................................................................................ 2–8
LAB Control Signals .............................................................................................................................. 2–9
Conclusion ............................................................................................................................................ 2–11
Document Revision History ............................................................................................................... 2–11
Introduction ............................................................................................................................................ 3–1
MultiTrack Interconnect ....................................................................................................................... 3–1
Conclusion ............................................................................................................................................ 3–11
Document Revision History ............................................................................................................... 3–11
Introduction ............................................................................................................................................ 4–1
Overview ................................................................................................................................................. 4–1
Memory Modes .................................................................................................................................... 4–10
Clocking Modes ................................................................................................................................... 4–17
Design Considerations ........................................................................................................................ 4–28
Topology ............................................................................................................................................ 2–8
LAB Interconnects ............................................................................................................................ 2–9
Row Interconnects ............................................................................................................................ 3–2
Column Interconnects ...................................................................................................................... 3–3
Device Routing ................................................................................................................................. 3–7
LAB Local Interconnects ................................................................................................................. 3–8
M9K Routing Interface .................................................................................................................... 3–9
Embedded Multiplier Routing Interface ..................................................................................... 3–10
Control Signals .................................................................................................................................. 4–3
Parity Bit Support ............................................................................................................................. 4–4
Byte Enable Support ........................................................................................................................ 4–4
Packed Mode Support ..................................................................................................................... 4–6
Address Clock Enable Support ...................................................................................................... 4–7
Mixed Width Support ...................................................................................................................... 4–9
Asynchronous Clear ........................................................................................................................ 4–9
Single-Port Mode ............................................................................................................................ 4–10
Simple Dual-Port Mode ................................................................................................................. 4–12
True Dual-Port Mode ..................................................................................................................... 4–13
Shift Register Mode ........................................................................................................................ 4–15
ROM Mode ...................................................................................................................................... 4–17
FIFO Buffer Mode ........................................................................................................................... 4–17
Independent Clock Mode .............................................................................................................. 4–18
Input/Output Clock Mode ........................................................................................................... 4–20
Read/Write Clock Mode ............................................................................................................... 4–23
Single-Clock Mode ......................................................................................................................... 4–25
Read-During-Write Operations .................................................................................................... 4–28
Conflict Resolution ......................................................................................................................... 4–31
Power-Up Conditions and Memory Initialization .................................................................... 4–32
Power Management ....................................................................................................................... 4–32
Cyclone III Device Handbook, Volume 1
Altera Corporation