ep3c120f780c8nes Altera Corporation, ep3c120f780c8nes Datasheet - Page 299

• Manufacturer Part Number: ep3c120f780c8nes
• Description: Cyclone Iii Device Family
• Manufacturer: Altera Corporation

Altera Corporation-Preliminary
March 2007
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Upon power-up, the Cyclone III devices go through a POR. The POR
delay is dependent on the MSEL pin settings which correspond to the
configuration scheme that you select. Depending on the configuration
scheme, either a fast POR time or a standard POR time is available. The
fast POR time is 3ms < T
standard POR time is 50ms < T
ramp rate. During POR, the device resets, holds nSTATUS low, and tri-
states all user I/O pins. Once the device successfully exits POR, all user
I/O pins continue to be tri-stated. The user I/O pins and dual-purpose
I/O pins have weak pull-up resistors which are always enabled (after
POR) before and during configuration.
For more information about the value of the weak pull-up resistors on
the I/O pins that are on before and during configuration, refer to the DC
and Switching Characteristics chapter in the Cyclone III Device Handbook.
The three stages in the configuration cycle are reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in the
reset stage. To initiate configuration, the MAX II device must drive the
nCONFIG pin from low-to-high.
1
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10 KΩ
pull-up resistor. Once nSTATUS is released, the device is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the MAX II device places the configuration data one byte at
a time on the DATA[7..0] pins.
The Cyclone III devices receive configuration data on the DATA[7..0]
pins and the clock is received on the DCLK pin. Data is latched into the
device on the rising edge of DCLK. Data is continuously clocked into the
target device until CONF_DONE goes high. The CONF_DONE pin goes high
one byte early in FPP configuration mode. The last byte is required for
serial configuration (AS and PS) modes. After the device has received the
next to last byte of the configuration data successfully, it releases the
open-drain CONF_DONE pin, which is pulled high by an external 10 KΩ
pull-up resistor. A low-to-high transition on CONF_DONE indicates
configuration is complete and initialization of the device can begin. The
CONF_DONE pin must have an external 10 KΩ pull-up resistor in order for
the device to initialize.
To begin configuration, power the V
the banks where the configuration and JTAG pins reside)
voltages to the appropriate voltage levels.
POR
< 9ms for fast configuration time. The
POR
< 200ms which has a lower power
Cyclone III Device Handbook, Volume 1
Fast Passive Parallel Configuration
CCINT
, V
CCA
, and V
CCIO
10–63
(for