ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 19

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
THEORY OF OPERATION
ANALOG INPUTS
The ADE7854 has seven analog inputs forming current and
voltage channels. The current channels consist of three pairs of
fully differential voltage inputs: IAP and IAN, IBP and IBN, ICP
and ICN. These voltage input pairs have a maximum
differential signal of ±0.5 V. The maximum common mode
signal allowed on the inputs is ±25 mV. Figure 10 presents a
schematic of the current channels inputs and their relation to
the maximum common mode voltage.
All inputs have a programmable gain amplifier (PGA) with
possible gain selection of 1, 2, 4, 8 or 16. The gain of IA, IB and
IC inputs is set in PGA1 bits of GAIN[15:0] register. See Table
33 for details on GAIN[15:0] register.
The voltage channel has three single-ended voltage inputs: VAP,
VBP, and VCP. These single-ended voltage inputs have a
maximum input voltage of ±0.5 V with respect to VN. In
addition, the maximum signal level on analog inputs for VxP
and VN is ±0.5 V with respect to AGND. The maximum
common mode signal allowed on the inputs is ±25 mV. Figure
12 presents a schematic of the voltage channels inputs and their
relation to the maximum common mode voltage.
All inputs have a programmable gain with possible gain
selection of 1, 2, 4, 8, or 16. The setting is done using PGA3 bits
in GAIN[15:0] register – see Table 33.
Figure 11 shows how the gain selection from GAIN[15:0]
register works in both current and voltage channels.
+500mV
-500mV
IxP, VxP
x=A,B,C
IxN, VN
V
CM
V
V
IN
1
Figure 10. Maximum input level, current channels, Gain=1
+V
2
Figure 11.PGA in current and voltage channels
K x V
+
-
IN
V
SELECTION
CM
GAIN
V
DIFFERENTIAL INPUT
1
+V
V
COMMON MODE
CM
+
+
2
-
-
=500mV MAX PEAK
=+/-25mV MAX
V
V
1
2
IAP, IBP or
IAN, IBN
or ICN
ICP
+
-
Rev. PrC| Page 19 of 71
ANALOG TO DIGITAL CONVERSION
The ADE7854 has six sigma-delta Analog to Digital Converters
(ADC). In PSM0 mode, all ADCs are active. In PSM3 mode,
the ADCs are powered down to minimize power consumption.
For simplicity, the block diagram in Figure 13 shows a first-
order Σ -Δ ADC. The converter is made up of the Σ -Δ
modulator and the digital low-pass filter.
A Σ - ∆ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7854, the sampling clock is equal to
1.024MHz (CLKIN/16). The 1-bit DAC in the feedback loop is
driven by the serial data stream. The DAC output is subtracted
from the input signal. If the loop gain is high enough, the
average value of the DAC output (and therefore the bit stream)
can approach that of the input signal level. For any given input
value in a single sampling interval, the data from the 1-bit ADC is
virtually meaningless. Only when a large number of samples are
averaged is a meaningful result obtained. This averaging is
carried out in the second part of the ADC, the digital low-pass
filter. By averaging a large number of bits from the modulator,
the low-pass filter can produce 24-bit data-words that are
proportional to the input signal level.
The Σ -Δ converter uses two techniques to achieve high
resolution from what is essentially a 1-bit conversion technique.
The first is oversampling. Oversampling means that the signal is
sampled at a rate (frequency), which is many times higher than
the bandwidth of interest. For example, the sampling rate in the
LOW-PASS FILTER
+500mV
-500mV
ANALOG
V
R
CM
C
Figure 12. Maximum input level, voltage channels, Gain=1
V
1
+
Figure 13. First-Order
–
INTEGRATOR
V
V
DIFFERENTIAL INPUT
1
REF
+V
V
COMMON MODE
CM
1-BIT DAC
+
+
2
-
-
=500mV MAX PEAK
=+/-25mV MAX
CLKIN/16
.....10100101.....
+
–
V
V
LATCHED
COMPARATOR
Σ
1
CM
-∆ ADC
VAP, VBP
or VCP
VN
ADE7854
LOW-PASS
DIGITAL
FILTER
+
-
24