ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 25

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
time base for various power quality measurements and in the
calibration process.
A zero-crossing is generated from the output of LPF1. The low
pass filter is intended to eliminate all harmonics of 50Hz and
60Hz systems and help identify the zero crossing events on the
fundamental components of both current and voltage channels.
The digital filter has a pole at 80Hz and is clocked at 256KHz.
As a result, there is a phase lag between the analog input signal
(one of IA, IB, IC, VA, VB and VC) and the output of LPF1. The
error in ZX detection is 0.07° for 50Hz systems (0.085° for 60Hz
systems). The phase lag response of LPF1 results in a time delay
of approximately 31.4° or 1.74msec (@ 50 Hz) between its input
and output. The overall delay between the zero crossing on the
analog inputs and ZX detection obtained after LPF1 is around
39.6° or 2.2 msec (@ 50 Hz). The ADC and HPF introduce the
additional delay. The LPF1 cannot be disabled to assure a good
resolution of the ZX detection. Figure 27 shows how the zero-
crossing signal is detected.
In order to provide further protection from noise, input signals
to the voltage channel with amplitude lower than 10% of full
scale do not generate zero crossing events at all. The current
channel ZX detection circuit is active for all input signals
independent of their amplitude.
The ADE7854 contains six zero crossing detection circuits, one
for each phase voltage and current channel. Each circuit drives
one flag in STATUS1[31:0] register. If circuit placed in phase A
voltage channel detects one zero crossing event, then bit 9
(ZXVA) in STATUS1[31:0] register is set to 1. Similarly, phase B
voltage circuit drives bit 10 (ZXVB), phase C voltage circuit
drives bit 11 (ZXVC) and circuits placed in the current channel
drive bit 12 (ZXIA), bit 13 (ZXIB) and bit 14 (ZXIC). If a ZX
detection bit is set in the MASK1[31:0] register, the
flag is set to 1. The status bit is cleared and
high by writing STATUS1 register with the status bit set to 1.
Zero-Crossing Timeout
Every zero-crossing detection circuit has an associated timeout
register. This register is loaded with the value written into 16-bit
ZXTOUT register and is decremented (1 LSB) every 62.5 μs
(16KHz clock). The register is reset to ZXTOUT value every
IRQ interrupt pin is driven low and the corresponding status
IA, IB, IC, IN
VA, VB, VC
Figure 27. Zero-Crossing Detection on Voltage and Current channels
1
or
PGA
REFERENCE
IA, IB, IC, IN
VA, VB, VC
ADC
or
0.855
DSP
GAIN[23:0]
0V
1
ZX
HPFDIS[23:0]
39.6 deg or 2.2msec
HPF
ZX
@ 50Hz
IRQ pin is set back
ZX
1
LPF1
LPF1 output
ZX
DETECTION
ZX
Rev. PrC| Page 25 of 71
time a zero crossing is detected. The default value of this
register is 0xFFFF. If the timeout register decrements to 0 before
a zero crossing is detected, then one of bits 8-3 of
STATUS1[31:0] register is set to 1. Bit 3 (ZXTOVA), bit 4
(ZXTOVB) and bit 5 (ZXTOVC) refer to phases A, B and C of
the voltage channel, bit 6 (ZXTOIA), bit 7 (ZXTOIB), bit 8
(ZXTOIC) refer to phases A, B and C of the current channel. If
a ZXTOUT bit is set in the MASK1[31:0] register, the
bit is set to 1. The status bit is cleared and
high by writing STATUS1 register with the status bit set to 1.
The resolution of ZXTOUT register is 62.5 μs (16KHz clock)
per LSB. Thus, the maximum time-out period for an interrupt
is 4.096seconds: 2
Figure 28 shows the mechanism of the zero-crossing timeout
detection when the voltage or the current signal stays at a fixed
dc level for more than 62.5 x ZXTOUT μs.
Phase Sequence Detection
The ADE7854 has an on-chip phase sequence error detection
circuit. This detection works on phase voltages and considers
only the zero crossings determined by their negative to positive
transitions. The regular succession of these zero crossing events
is phase A followed by phase B followed by phase C (see Figure
30). If the sequence of zero crossing events is instead phase A,
followed by phase C followed by phase B, then bit 19 (SEQERR)
in STATUS1[31:0] register is set. If bit 19 (SEQERR) in
MASK1[31:0] register is set to 1 and a phase sequence error
event is triggered, then
status bit is cleared and
STATUS1 register with the status bit SEQERR set to 1.
The phase sequence error detection circuit is functional only
when the ADE7854 is connected in a 3 phase 4 wire 3 voltage
sensors configuration (bits 5,4 CONSEL in ACCMODE[7:0] set
to 00). In all other configurations, only two voltage sensors are
IRQ interrupt pin is driven low when the corresponding status
STATUS1[31:0],x=V,A
IRQ1\ interrupt pin
1
REGISTER VALUE
ZXTOxy flag in
16-bit INTERNAL
y=A,B,C
Voltage
Current
Signal
or
Figure 28. Zero-Crossing Timeout Detection
ZXTOUT
16
/16KHz.
0V
IRQ interrupt pin is driven low. The
IRQ pin is set back high by writing
1
1
IRQ pin is set back
1
ADE7854