ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 40

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

ADE7854
Bit 4 (VAEHF) in STATUS0[31:0] register is set when bit 30 of
one of xVAHR, x=A,B,C registers changes, signifying one of
these registers is half full. As the apparent power is always
positive and xVAHR, x=A,B,C registers are signed, the VA-hr
registers become half full when they increment from
0x3FFFFFFF to 0x4000 0000. Interrupts attached to bit VAEHF
in STATUS0[31:0] register may be enabled by setting bit 4 in
MASK0[31:0] register. If enabled, the
the status bit is set to 1 whenever one of the energy registers
xVAHR, x=A,B,C becomes half full. The status bit is cleared and
corresponding bit set to 1.
Setting bit 6 (RSTREAD) of LCYMODE[7:0] register enables a
read-with-reset for all va-hr accumulation registers, that is, the
registers are reset to 0 after a read operation.
Integration Time Under Steady Load
The discrete time sample period (T) for the accumulation
register is 125μs (1/8 KHz). With full-scale pure sinusoidal
signals on the analog inputs, the average word value representing
the apparent power is PMAX. If the VATHR threshold is set at
PMAX level, this means the DSP generates a pulse that is added
at VA-hr registers every 125 μs.
The maximum value that can be stored in the va-hr
accumulation register before it overflows is 2
0x7FFFFFFF. The integration time is calculated as
Energy Accumulation Mode
The apparent power accumulated in each VA-hr accumulation
register (AVAHR[31:0], BVAHR[31:0] or CVAHR[31:0])
depends on the configuration of bits 5,4 (CONSEL) in the
ACCMODE[7:0] register. The different configurations are
described in Table 14.
Table 14. Inputs to VA-Hr Accumulation Registers
CONSEL[1,0]
00
01
10
11
Line Cycle Apparent Energy Accumulation Mode
As mentioned in Line Cycle Active Energy Accumulation Mode
section, in line cycle energy accumulation mode, the energy
accumulation can be synchronized to the voltage channel zero
crossings so that apparent energy can be accumulated over an
integral number of half line cycles. In this mode, the ADE7854
transfers the apparent energy accumulated in the 32-bit internal
IRQ pin is set back high by writing STATUS0 register with the
Time
0
=
0
7 x
FFF
,
AVAHR
AVRMS ×
AIRMS
AVRMS ×
AIRMS
AVRMS ×
AIRMS
AVRMS ×
AIRMS
FFFF
×
125
μ
s
=
74
BVAHR
BVRMS ×
BIRMS
0
BVRMS ×
BIRMS
VB=-VA-VC
BVRMS ×
BIRMS
VB=-VA
h
33
IRQ pin is set low and
min
0
55
31
s
− 1 or
CVAHR
CVRMS ×
CIRMS
CVRMS ×
CIRMS
CVRMS ×
CIRMS
CVRMS ×
CIRMS
(31)
Rev. PrC| Page 40 of 71
accumulation registers into xVAHR[31:0], x=A,B,C registers
after an integral number of line cycles, as shown in Figure 50.
The number of half line cycles is specified in the
LINECYC[15:0] register.
The line cycle apparent energy accumulation mode is activated
by setting bit 2 (LVA) in the LCYCMODE[7:0] register. The
apparent energy accumulated over an integer number of zero
crossings is written to the VA-hr accumulation registers after
the LINECYC number of zero crossings is detected. When
using the line cycle accumulation mode, bit 6 (RSTREAD) of
the LCYCMODE[7:0] register should be set to Logic 0 because
the read with reset of VA-hr registers is not available in this
mode.
Phase A, Phase B, and Phase C zero crossings are, respectively,
included when counting the number of half-line cycles by
setting bits 5,4,3 (ZXSEL) in the LCYCMODE[7:0] register. Any
combination of the zero crossings from all three phases can be
used for counting the zero crossing. Only one phase should be
selected at a time for inclusion in the zero crossings count
during calibration.
For details on setting LINECYC[15:0] register and the interrupt
LENERGY associated with the line cycle accumulation mode,
see Line Cycle Active Energy Accumulation Mode section.
WAVEFORM SAMPLING MODE
The waveform samples of the current and voltage waveform, the
active and apparent power multiplier outputs are stored every
125μsec (8KHz rate) into 24-bit signed registers that may be
accessed through various serial ports of the ADE7854. Table 15
presents the list of the registers and their description.
Table 15. Waveform registers list
Register
IAWV
IBWV
AVRMS
AIRMS
Figure 50. ADE7854 Line Cycle Apparent Energy Accumulation Mode
ZERO CROSSING
ZERO CROSSING
ZERO CROSSING
DETECTION
DETECTION
DETECTION
(PHASE A)
(PHASE B)
(PHASE C)
Description
Phase A current
Phase B current
LCYCMODE[7:0]
LCYCMODE[7:0]
LCYCMODE[7:0]
AVAGAIN
ZXSEL[0] in
ZXSEL[1] in
ZXSEL[2] in
Σ
Preliminary Technical Data
Σ
VAHR[47:0]
56 bits
AWATT
Register
BWATT
Σ
Description
Phase A active
power
Phase B active
LINECYC[15:0]
CALIBRATION
CONTROL
32 bit register
AVAHR[31:0]