ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 44

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

ADE7854
NO-LOAD CONDITION
The no-load condition is defined in metering equipment
standards as occurring when the voltage is applied to the meter
and no current flows in the current circuit. To eliminate any
creep effects in the meter, the ADE7854 contains two separate
no-load detection circuits: one related to the total active powers,
and one related to the apparent powers.
No-load detection based on total active power
This no-load condition is triggered when the absolute values of
phase total active powers are less than or equal to a threshold
indicated in APNOLOAD[23:0] signed 24-bit register. In this
case, the total active energy on that phase is not accumulated
and no CF pulses are generated based on it. APNOLOAD[24:0]
represents the positive no-load level of total active power
relative to PMAX, the maximum total active power obtained
when full scale voltages and currents are provided at ADC
inputs. The expression used to compute APNOLOAD[23:0]
signed 24-bit value is:
where: PMAX=33,516,139=0x1FF6A6B, the instantaneous
power computed when the ADC inputs are at full scale
U
ADC inputs are at full scale.
U
I
measuring.
When APNOLOAD is set to negative values, the no-load
detection circuit is disabled. Note that to ensure the good
functionality of this no-load circuit, the 24-bit VARNOLOAD
register placed at address 0x43B2 must be set at 0x800000.
As previously stated, the serial ports of the ADE7854 work on
32, 16 or 8-bit words and the DSP works on 28 bits.
APNOLOAD and VARNOLOAD 24-bit signed registers are
accessed as 32-bit registers with 4 most significant bits padded
with 0s and sign extended to 28 bits. See Figure 16 for details.
Bit 0 (NLOAD) in STATUS1[31:0] register is set when this no-
load condition in one of the three phases is triggered. Bits 2, 1, 0
(NLPHASE[2:0]) in PHNOLOAD[15:0] register indicate the
state of all phases relative to no-load condition and are set
simultaneously with bit NLOAD in STATUS1[31:0].
NLPHASE[0] indicates the state of phase A , NLPHASE[1] the
state of phase B, NLPHASE[2] the state of phase C. When bit
NLPHASE[x], x=0, 1, 2 is cleared to 0, it means the phase is out
of no-load condition. When set to 1, it means the phase is in
no-load condition.
An interrupt attached to the bit 0 (NLOAD) in STATUS1[31:0]
may be enabled by setting bit 0 in MASK1[31:0] register. If
enabled, the
APNOLOAD
noload
FS
n
, the nominal rms value of phase voltage.
, I
, the minimum rms value of phase current the meter starts
FS
, the rms values of phase voltages and currents when the
IRQ pin is set low and the status bit is set to 1
=
U
U
1
FS
n
⋅
I
noload
I
FS
⋅
PMAX
(33)
Rev. PrC| Page 44 of 71
whenever one of three phases enters or exits this no-load
condition. To find the phase that triggered the interrupt,
PHNOLOAD[15:0] register is read immediately after reading
STATUS1[31:0]. Then the status bit is cleared and
set back high by writing STATUS1 register with the
corresponding bit set to 1.
No-load detection based on apparent power
This no-load condition is triggered when the absolute value of
phase apparent power is less than or equal to the threshold
indicated in VANOLOAD[23:0] 24-bit signed register. In this
case, the apparent energy of that phase is not accumulated and
no CF pulses are generated based on this energy. VANOLOAD
represents the positive no-load level of apparent power relative
to PMAX, the maximum apparent power obtained when full
scale voltages and currents are provided at ADC inputs. The
expression used to compute VANOLOAD[23:0] signed 24-bit
value is:
where: PMAX=33,516,139=0x1FF6A6B, the instantaneous
apparent power computed when the ADC inputs are at full scale
U
ADC inputs are at full scale.
U
I
measuring.
When VANOLOAD[23:0] is set to negative values, the no load
detection circuit is disabled.
As previously stated, the serial ports of the ADE7854 work on
32, 16 or 8-bit words and the DSP works on 28 bits. Similar to
registers presented inFigure 16, VANOLOAD 24-bit signed
register is accessed as a 32-bit registers with 4 most significant
bits padded with 0s and sign extended to 28 bits.
Bit 2 (VANLOAD) in STATUS1[31:0] register is set when this
no-load condition in one of the three phases is triggered. Bits 8,
7, 6 (VANLPHASE[2:0]) in PHNOLOAD[15:0] register indicate
the state of all phases relative to no-load condition and are set
simultaneously with bit VANLOAD in STATUS1[31:0].
VANLPHASE[0] indicates the state of phase A ,
VANLPHASE[1] the state of phase B, VANLPHASE[2] the state
of phase C. When bit VANLPHASE[x], x=0, 1, 2 is cleared to 0,
it means the phase is out of no-load condition. When set to 1, it
means the phase is in no-load condition.
An interrupt attached to the bit 2 (VANLOAD) in
STATUS1[31:0] may be enabled by setting bit 2 in
MASK1[31:0] register. If enabled, the
the status bit is set to 1 whenever one of three phases enters or
exits this no-load condition. To find the phase that triggered the
interrupt, PHNOLOAD[15:0] register is read immediately after
reading STATUS1[31:0]. Then the status bit is cleared and
VANOLOAD
noload
FS
n
, the nominal rms value of phase voltage.
, I
, the minimum rms value of phase current the meter starts
FS
, the rms values of phase voltages and currents when the
=
U
U
FS
n
Preliminary Technical Data
⋅
I
noload
I
FS
⋅
PMAX
IRQ pin is set low and
1
IRQ pin is
1