ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 43

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Bits 14, 13, 12 (CF3LATCH, CF2LATCH and CF1LATCH) of
CFMODE[15:0] register enable this process when set to 1.
When cleared to 0, the default state, no latch occurs. The
process is available even if the CFx output is not enabled by
CFxDIS bits in CFMODE[15:0].
CF outputs for various accumulation modes
The bits 1, 0 (WATTACC[1:0]) in ACCMODE[7:0] register
determine the accumulation modes of the total active powers
when signals proportional to the total active powers are chosen
at CFx pins (bits CFxSEL[2:0], x=1,2,3 in CFMODE[15:0]
register are equal to 000 or to 011). When WATTACC[1:0]=00,
the default value, the active powers are sign accumulated before
entering the energy to frequency converter. Figure 54 presents
the way signed active power accumulation works. Note that in
this mode, the CF pulses are perfectly synchronized with the
active energy accumulated in watt-hr registers because the
powers are sign accumulated in both data paths.
When WATTACC[1:0]=11, the active powers are accumulated
in absolute mode. When the powers are negative, they change
sign and are accumulated together with the positive power.
Figure 55 presents the way absolute active power accumulation
works. Note that in this mode, the watt-hr registers continue to
accumulate active powers in signed mode, even if the CF pulses
are generated based on the absolute accumulation mode.
Sign of sum of phase powers in CFx data path
The ADE7854 has a sign detection circuitry for the sum of
phase powers that are used in CFx, x=1, 2, 3 data path. As seen
in the beginning of ENERGY to FREQUENCY CONVERSION
chapter, the energy accumulation in CFx data path is executed
in two stages. Every time a sign change is detected in the energy
accumulation at the end of the first stage, that is after the energy
accumulated into the 55 bit accumulator reaches one of
THRESHOLD
THRESHOLD
in STATUS0
REVAPx bit
xWSIGN bit
in PHSIGN
NO-LOAD
NO-LOAD
ENERGY
POWER
ACTIVE
ACTIVE
Figure 54. Active power signed accumulation mode
SIGN=POSITIVE
APNOLOAD
POS
NEG
POS
NEG
Rev. PrC| Page 43 of 71
WTHR[47:0] or VATHR[47:0] thresholds, a dedicated interrupt
may be triggered synchronously with the corresponding CF
pulse. The sign of each sum may be read in PHSIGN[15:0]
register.
Bits 18, 13, 9 (REVPSUM3, REVPSUM2, and respectively
REVPSUM1) of STATUS0[31:0] register are set to 1 when a sign
change of the sum of powers in CF3, CF2 or CF1 data paths
occurs. To correlate these events with the pulses generated at
CFx pins, after a sign change occurs, bits REVPSUM3,
REVPSUM2 and REVPSUM1 are set in the same moment in
which a high to low transition at CF3, CF2 and respectively CF1
pin occurs.
Bits 8, 7, 3 (SUM3SIGN, SUM2SIGN and respectively
SUM1SIGN) of PHSIGN[15:0] register are set in the same
moment with bits REVPSUM3, REVPSUM2 and REVPSUM1
and indicate the sign of the sum of phase powers. When cleared
to 0, the sum is positive. When set to 1, the sum is negative.
Interrupts attached to the bits 18, 13, 9 (REVPSUM3,
REVPSUM2, and respectively REVPSUM1) in STATUS0[31:0]
register may be enabled by setting bits 18, 13 , 9 in
MASK0[31:0] register. If enabled, the
the status bit is set to 1 whenever a change of sign occurs. To
find the phase that triggered the interrupt, PHSIGN[15:0]
register is read immediately after reading STATUS0[31:0]. Then
the status bit is cleared and
STATUS0 register with the corresponding bit set to 1.
THRESHOLD
THRESHOLD
in STATUS0
REVAPx bit
xWSIGN bit
in PHSIGN
NO-LOAD
NO-LOAD
ENERGY
ACTIVE
ACTIVE
POWER
Figure 55. Active power absolute accumulation mode
SIGN=POSITIVE
APNOLOAD
IRQ pin is set back high by writing
0
POS
IRQ pin is set low and
0
NEG
POS
ADE7854
NEG