ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 46

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

INTERRUPTS
The ADE7854 has two interrupt pins,
them is managed by a 32-bit interrupt mask register,
MASK0[31:0], respective MASK1[31:0]. To enable an interrupt,
a bit in MASKx[31:0] register has to be set to 1. To disable it, the
bit has to be cleared to 0. Two 32-bit status registers,
STATUS0[31:0] and STATUS1[31:0] are associated with the
interrupts. When an interrupt event occurs in the ADE7854, the
corresponding flag in the interrupt status register is set to a
Logic 1 (see Table 26 and Table 27). If the mask bit for this
interrupt in the interrupt mask register is Logic 1, then the
status register are set irrespective of the state of the mask bits.
To determine the source of the interrupt, the MCU should
perform a read of corresponding STATUSx register and identify
which bit is 1. To erase the flag in the status register, STATUSx
should be written back with the flag set to 1. Practically, after an
interrupt pin goes low, the status register is read and the source
of the interrupt is identified. Then, the status register is written
back without any change to cancel the status flag. The IRQx pin
remains low until the status flag is cancelled.
By default, all interrupts are disabled. RSTDONE interrupt is an
exception. This interrupt can never be masked (disabled) and
therefore bit 15 (RSTDONE) in MASK1[31:0] register does not
have any functionality.
(RSTDONE) in STATUS1[31:0] is set to 1 whenever a power up
or a hardware/software reset process ends. To cancel the status
flag, STATUS1[31:0] register has to be written with bit
15(RSTDONE) set to 1.
Certain interrupts are used in conjunction with other status
registers: bits 0 (NLOAD) and 2 (VANLOAD) in MASK1[31:0]
work in conjunction with status bits in PHNOLAD[15:0]. Bits
16, (SAG), 17 (OI) and 18 (OV) in MASK1[31:0] work with
status bits in PHSTATUS[15:0]. Bits 23 (PKI) and 24 (PKV) in
MASK1[31:0] work with status bits in IPEAK[31:0] and
respectively, VPEAK[31:0]. Bits 6, 7, 8 (REVAPx, x=A, B, C)
and 9, 13, 18 (REVPSUMx) in MASK0[31:0] work with status
bits in PHSIGN[15:0]. When STATUSx[31:0] register is read
Preliminary Technical Data
IRQx logic output goes active low. The flag bits in the interrupt
SEQUENCE
PROGRAM
IRQx
t
1
to ISR
JUMP
IRQ pin always goes low and bit 15
INTERRUPT
GLOBAL
1
MASK
IRQ and
CLEAR MCU
INTERRUPT
FLAG
0
IRQ . Each of
Figure 58. ADE7854 interrupt management
1
STATUSx
READ
Rev. PrC | Page 46 of 71
STATUSx
WRITE
BACK
t
2
and one of these bits is set to 1, the status register associated
with the bit is immediately read to identify the phase that
triggered the interrupt and only then STATUSx[31:0] is written
back with the bit set to 1 to cancel the status flag.
Using the Interrupts with an MCU
Figure 58 shows a timing diagram that illustrates a suggested
implementation of the ADE7854 interrupt management using
an MCU. At time t
one or more interrupt events have occurred in the ADE7854.
The IRQx pin should be tied to a negative-edge-triggered
external interrupt on the MCU. On detection of the negative
edge, the MCU should be configured to start executing its
interrupt service routine (ISR). On entering the ISR, all
interrupts should be disabled using the global interrupt mask
bit. At this point, the MCU external interrupt flag can be
cleared to capture interrupt events that occur during the current
ISR. When the MCU interrupt flag is cleared, a read from
STATUSx, the interrupt status register is carried out. The
interrupt status register content is used to determine the source
of the interrupt(s) and hence the appropriate action to be taken.
Then, the same STATUSx content is written back into the
ADE7854 to clear the status flag(s) and reset IRQx line to logic
high (t
(t
being set again.
On returning from the ISR, the global interrupt mask bit is
cleared (same instruction cycle) and the external interrupt flag
uses the MCU to jump to its ISR once again. This ensures that
the MCU does not miss any external interrupts.
Figure 59 shows a recommended timing diagram when status
bits in STATUSx registers work in conjunction with bits in
other registers. Same as above, when IRQx pin goes active low,
STATUSx register is read and if one of these bits is 1, then a
second status register is read immediately to identify the phase
that triggered the interrupt. The name PHx in the figure
denotes one of PHSTATUS, IPEAK, VPEAK or PHSIGN
registers. Then STATUSx register is afterwards written back to
clear the status flag(s).
(BASED ON STATUSx CONTENTS)
3
) that event is recorded by the MCU external interrupt flag
2
). If a subsequent interrupt event occurs during the ISR
ISR ACTION
1
, IRQx pin goes active low indicating that
t
3
MCU INTERRUPT
GLOBAL INTERRUPT
FLAG SET
MASK RESET
ISR RETURN
ADE7854
to ISR
JUMP