ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 39

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
The output is scaled by –50% by writing 0xC00000 to the VA
gain registers and increased by +50% by writing 0x400000 to
them. These registers can be used to calibrate the apparent
power (or energy) calculation in the ADE7854 for each phase.
As previously stated, the serial ports of the ADE7854 work on
32, 16 or 8-bit words and the DSP works on 28 bits. Similar to
registers presented in Figure 16, AVAGAIN, BVAGAIN,
CVAGAIN 24-bit registers are accessed as 32-bit registers with 4
most significant bits padded with 0s and sign extended to 28
bits.
Apparent Power Offset Calibration
Each rms measurement includes an offset compensation register
to calibrate and eliminate the dc component in the rms value
(see the Root Mean Square Measurement section). The voltage
and current rms values are then multiplied together in the
apparent power signal processing. As no additional offsets are
created in the multiplication of the rms values, there is no specific
offset compensation in the apparent power signal processing. The
offset compensation of the apparent power measurement in each
phase should be done by calibrating each individual rms
measurement.
Apparent Power Calculation using VNOM
The ADE7854 may compute the apparent power multiplying
the phase rms current by an rms voltage introduced externally
in VNOM[23:0] 24-bit unsigned register. When one of bits 13,
12, 11 (VNOMCEN, VNOMBEN, VNOMAEN) in
COMPMODE[15:0] register is set to 1, the apparent power in
the corresponding phase (phase x for VNOMxEN, x=A,B,C) is
computed in this way. When bits VNOMxEN are cleared to 0,
the default value, then the arithmetic apparent power is
computed.
VNOM[23:0] register contains a number determined by U, the
desired rms voltage and
voltage when the ADC inputs are at full scale:
Usually U is the nominal phase rms voltage.
As previously stated, the serial ports of the ADE7854 work on
32, 16 or 8-bit words. Similar to the register presented in Figure
17, VNOM 24-bit register is accessed as a 32-bit register with 8
most significant bits padded with 0s.
Apparent Energy Calculation
Apparent energy is defined as the integral of apparent power.
Average
VRMS
VNOM
ApparentEn
×
=
Apparent
IRMS
U
U
ergy
FS
×
⋅
, 4
=
⎛
⎜
⎝
191
Power
1
∫
+
t s
,
) (
400
VAGAIN
U
dt
=
FS
, the rms value of the phase
2
23
Register
⎞
⎟
⎠
(29)
(27)
(28)
Rev. PrC| Page 39 of 71
Similar to active and reactive powers, the ADE7854 achieves
the integration of the apparent power signal in two stages (see
Figure 49). The first stage is done inside the DSP: every 125μsec
(8KHz frequency), the instantaneous phase apparent power is
accumulated into an internal 56-bit register. When a threshold
is reached, a pulse is generated at processor port and the
threshold is subtracted from the internal register. The second
stage is done outside the DSP and consists in accumulating the
pulses generated by the processor into internal 32-bit
accumulation registers. The content of these registers is
transferred to va-hr registers xVAHR[31:0], x=A, B, C when
these registers are accessed.
Figure 46 from the Active Energy Calculation section explains
this process. The VATHR[47:0] 48-bit register contains the
threshold. Its value depends on how much energy is assigned to
1LSB of VA-hour registers. Let’s suppose a derivative of VAh
[10
VATHR may be computed using the following expression:
where:
PMAX=33,516,139=0x1FF6A6B, the instantaneous power
computed when the ADC inputs are at full scale.
f
instantaneous power.
U
the ADC inputs are at full scale.
The VATHR[47:0] is a 48-bit register. As previously stated, the
serial ports of the ADE7854 work on 32, 16 or 8-bit words.
Similar to the WTHR[47:0] register presented in Figure 47,
VATHR[47:0] is accessed as two 32-bit registers
(VATHR1[31:0] and VATHR0[31:0]), each having 8 most
significant bits padded with 0s.
integration in continuous time following the description in
expression (30).
where:
n is the discrete time sample number.
T is the sample period.
In the ADE7854, the phase apparent powers are accumulated in
AVAHR[31:0], BVAHR[31:0] and CVAHR[31:0] 32-bit signed
registers. The apparent energy register content can roll over to
full-scale negative (0x80000000) and continue increasing in
value when the apparent power is positive. Conversely, if
because of offset compensation in rms data path, the apparent
power is negative, the energy register would under flow to full-
scale positive (0x7FFFFFFF) and continue decreasing in value.
VATHR
This discrete time accumulation or summation is equivalent to
ApparentEn
s
=8KHz is the frequency with which the DSP computes the
FS
n
, I
VAh], n an integer, is desired as 1LSB of VAHR. Then
FS
are the rms values of phase voltages and currents when
=
PMAX
ergy
U
=
⋅
∫
f
FS
s
s
⋅
( )
⋅
3600
I
t
FS
dt
=
⋅
10
Lim
T
n
→
0
⎧
⎨
⎩
n
∑
∞
=
0
s
( )
nT
×
T
⎫
⎬
⎭
ADE7854
(30)