ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 48

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

ADE7854
byte received. The address byte is similar to the address byte of a
write operation and is equal to 0x70 (See I2C Write Operation
section for details). After the last byte of the register address has
been sent and it has been acknowledged by the ADE7854, the
second stage begins with the master generating a new START
condition followed by an address byte. The most significant 7
bits of this address byte constitute the address of the ADE7854
and they are equal to b#0111000. Bit 0 of the address byte is
READ/ WRITE bit. Because this is a read operation, it has to be
set to 1, so the first byte of the read operation is 0x71. After this
byte is received, the ADE7854 generates an acknowledge. Then
the ADE7854 sends the value of the register and after every 8
bits are received, the master generates an acknowledge. All the
bytes are sent with the most significant bit first. As registers
may have 8, 16 or 32 bits, after the last bit of the register is
received , the master does not acknowledge the transfer, but
does generate a STOP condition.
SPI Compatible Interface
The Serial Peripheral Interface (SPI) of the ADE7854 is always a
slave of the communication and consists in four pins: SCLK,
MOSI, MISO and SS . The serial clock for a data transfer is
applied at the SCLK logic input. This logic input has a Schmitt
trigger input structure that allows slow rising (and falling) clock
S
T
A
R
T
S 0 1 1 1 0 0 0
slave address
0
A
C
K
15
MS 8 bits of reg
address
8
A
C
K
7
LS 8 bits of reg
address
Figure 60. I
0
A
C
K
2
C Write Operation of a 32 bit register
Rev. PrC| Page 48 of 71
31
Byte3 (MS) of reg
ADE7854/ADE7858
ACK generated by
edges to be used. All data transfer operations are synchronized
to the serial clock. Data is shifted into the ADE7854 at the
MOSI logic input on the falling edge of SCLK. Data is shifted
out of the ADE7854 at the MISO logic output on a rising edge
of SCLK. The most significant bit of the word is shifted in and
out first. The maximum serial clock frequency supported by
this interface is 2.5MHz. MISO stays in high impedance when
no data is transmitted from the ADE7854. Figure 62 presents
details of the connection between ADE7854 SPI and a master
device containing an SPI interface.
The SS logic input is the chip select input. This input is used
when multiple devices share the serial bus. The SS input
should be driven low for the entire data transfer operation.
Bringing SS high during a data transfer operation aborts the
transfer and places the serial bus in a high impedance state. A
new transfer can then be initiated by bringing the SS logic
input back low. However, because aborting a data transfer
before completion leaves the accessed register in a state that
cannot be guaranteed, every time a register is written, its value
should be verified by reading it back.
The protocol is similar to the protocol used in I
16
A
C
K
15
Byte2 of reg
Preliminary Technical Data
8
A
C
K
7
Byte1 of reg
0
A
C
K
7
Byte0 (LS) of reg
2
C interface.
0
A
C
K
S
T
O
P
S