ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 45

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
corresponding bit set to 1.
CHECKSUM REGISTER
The ADE7854 has a checksum 32-bit register
CHECKSUM[31:0] that ensures certain very important
configuration registers maintain their desired value during
normal power mode PSM0.
The registers covered by this register are MASK0[31:0],
MASK1[31:0], COMPMODE[15:0], GAIN[15:0],
CFMODE[15:0], CF1DEN[15:0], CF2DEN[15:0],
CF3DEN[15:0], CONFIG[15:0], MMODE[7:0],
ACCMODE[7:0], LCYCMODE[7:0], HSDC_CFG[7:0] and
other six 8-bit reserved internal registers that always have
default values. The ADE7854 computes the cyclic redundancy
check (CRC) based on the IEEE802.3 standard. The registers
are introduced one by one into a linear feedback shift register
(LFSR) based generator starting with the less significant bit (as
presented in Figure 56). The 32-bit result is written in
CHECKSUM[31:0] register. After power up or a
hardware/software reset, the CRC is computed on the default
values of the registers. The result is 0x2689B124.
Figure 57 presents how LFSR works. Bits a
the bits from the list of registers presented above. a
significant bit of the first internal register to enter LFSR, a
the most significant bit of MASK0[31:0] register, the last
register to enter LFSR. The equations that govern LFSR are
presented below:
b
CRC. b
g
polynomial defined by IEEE802.3 standard:
IRQ pin is set back high by writing STATUS1 register with the
31
255
i
i
(0) =1, i=0, 1, 2,…, 31, the initial state of the bits that form the
, i=0, 1, 2,…, 31 are the coefficients of the generating
LFSR
MASK0
1
g
248
0
0
is the less significant bit, b
0
31
MASK1
b
240
0
0
15
COMPMODE
232
0
g
+
15
1
GAIN
31
224
is the most significant.
0
Figure 57.LFSR generator used in CHECKSUM[31:0] register calculation
15
CFMODE
b
0
, a
1
1
,…, a
216
0
Figure 56. CHECKSUM[31:0] register calculation
0
255
is the less
represent
g
+
2
7
internal reg
255
Rev. PrC| Page 45 of 71
is
40
0
7
internal reg
b
2
32
All the other g
The operations ⊕ and ⋅ represent the logic XOR and AND.
The equations
2,…, 256. The value written into CHECKSUM[31:0] register
contains the bits b
after the bits from the reserved internal register have passed
through LFSR is 0x3A7ABC72. It is obtained at step j=48.
Two different approaches may be followed in using the
CHECKSUM register. One is to compute the CRC based on the
relations
CHECKSUM register. Another is to periodically read the
CHECKSUM[31:0] register. If two consecutive readings differ,
then it may be safely assumed that one of the registers has
changed value and therefore, the ADE7854 has changed
configuration. The recommended response is to initiate a
hardware/software reset that sets the values of all registers to the
default, including the reserved ones, and then reinitialize the
configuration registers.
0
G
+
g
g
FB
b
b
0
8
0
i
(
x
7
internal reg
) j (
) x
) j (
) j (
=
=
8
g
+
g
g
=
=
+
=
=
1
10
3
x
FB
x
a
FB
7
=
32
(34
24
j
=
−
0
+
) j (
g
) j (
1
g
+
2
) -
7
x
internal reg
⊕
11
⋅
⋅
x
5
=
g
g
i
b
(36
(38
26
+
i
=
coefficients are equal to 0.
0
g
31
⊕
x
4
g
+
),
) and then compare the value against the
j (
i
4
(256),i=0, 1,…, 31. The value of the CRC
12
b
=
16
x
(37
0
−
+
i
23
g
−
=
) 1
1
7
internal reg
x
) and
5
a
j (
+
g
2
=
255
16
−
x
+
g
1
22
x
=
7
i ),
g
,a
(38
+
+
+
g
=
8
31
0
1
254
=
22
) have to be repeated for j=1,
x
1
7
7
internal reg
1
16
2 ,
=
,...,a
+
3 ,
g
x
26
,...,
12
0
0
=
31
2
b
+
,a
1
31
x
1
11
,a
+
+
0
x
10
ADE7854
+
generator
LFSR
+
(36)
(38)
(37)
(34)
(35)
FB