ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 62

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

ADE7854
Table 28. MASK0 register (address 0xE50A)
Bit
Location
0
1-3
4
5
6
7
8
9
10-12
13
14
15
16
17
18
31-18
Table 29. MASK1 register (address 0xE50B)
Bit
Location
0
1
2
3
4
5
6
7
8
9
10
11
12
Bit
Mnemonic
AEHF
Reserved
VAEHF
LENERGY
REVAPA
REVAPB
REVAPC
REVPSUM1
Reserved
REVPSUM2
CF1
CF2
CF3
DREADY
REVPSUM3
Reserved
Bit
Mnemonic
NLOAD
Reserved
VANLOAD
ZXTOVA
ZXTOVB
ZXTOVC
ZXTOIA
ZXTOIB
ZXTOIC
ZXVA
ZXVB
ZXVC
ZXIA
Default
value
0
000
0
0
0
0
0
0
000
0
0
0
00 0000
0000
0000
Default
value
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
These bits do not manage any functionality.
When this bit is set to 1, it enables an interrupt when the phase B active power changes sign.
When this bit is set to 1, it indicates that the phase C active power changes sign.
These bits do not manage any functionality.
When this bit is set to 1, it enables an interrupt when bit 30 of any one of the total active energy
registers AWATTHR, BWATTHR, CWATTHR changes.
When this bit is set to 1, it enables an interrupt when bit 30 of any one of the apparent energy
registers AVAHR, BVAHR, CVAHR changes.
When this bit is set to 1, in line energy accumulation mode, it enables an interrupt at the end of an
integration over an integer number of half line cycles set in LINECYC[15:0] register.
When this bit is set to 1, it enables an interrupt when the phase A active power register changes
sign.
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF1 data
path changes sign.
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF2 data
path changes sign.
When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF1 pin, that
is an active low pulse is generated. The interrupt may be enabled even if the CF1 output is disabled
by setting bit 9 (CF1DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF1 pin is
determined by bits 2-0 (CF1SEL) in CFMODE[15:0] register (see Table 34).
When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF2 pin, that
is an active low pulse is generated. The interrupt may be enabled even if the CF2 output is disabled
by setting bit 10 (CF2DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF2 pin is
determined by bits 5-3 (CF2SEL) in CFMODE[15:0] register (see Table 34).
When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF3 pin, that
is an active low pulse is generated. The interrupt may be enabled even if the CF3 output is disabled
by setting bit 11 (CF3DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF3 pin is
determined by bits 8-6 (CF3SEL) in CFMODE[15:0] register (seeTable 34).
When this bit is set to 1, it enables an interrupt when all periodical (at 8KHz rate) DSP computations
finish.
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF3 data
path changes sign.
These bits do not manage any functionality.
Description
When this bit is set to 1, it enables an interrupt when at least one phase enters no-load condition
based on total active and reactive powers.
This bit does not manage any functionality.
When this bit is set to 1, it enables an interrupt when at least one phase enters no-load condition
based on apparent power.
When this bit is set to 1, it enables an interrupt when a zero crossing on phase A voltage misses.
When this bit is set to 1, it enables an interrupt when a zero crossing on phase B voltage misses.
When this bit is set to 1, it enables an interrupt when a zero crossing on phase C voltage misses.
When this bit is set to 1, it enables an interrupt when a zero crossing on phase A current misses.
When this bit is set to 1, it enables an interrupt when a zero crossing on phase B current is missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on phase C current is missing.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase A voltage.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase B voltage.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase C voltage.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase A current.
Rev. PrC| Page 62 of 71
Preliminary Technical Data