ade7854 Analog Devices, Inc., ade7854 Datasheet - Page 38

• Manufacturer Part Number: ade7854
• Description: Poly Phase Multifunction Energy Metering Ic With Neutral Current Measurement
• Manufacturer: Analog Devices, Inc.

ADE7854
The number of zero crossings is specified by the
LINECYC[15:0] 16-bit unsigned register. The ADE7854 can
accumulate active power for up to 65535 combined zero
crossings. Note that the internal zero-crossing counter is always
active. By setting bit 0 (LWATT) in LCYCMODE[7:0] register,
the first energy accumulation result is, therefore, incorrect.
Writing to the LINECYC[15:0] register when the LWATT bit is
set resets the zero-crossing counter, thus ensuring that the first
energy accumulation result is accurate.
At the end of an energy calibration cycle, the bit 5 (LENERGY)
in the STATUS0[31:0]register is set. If the corresponding mask
bit in the MASK0[31:0] interrupt mask register is enabled, the
corresponding bit set to 1.
Because the active power is integrated on an integer number of
half-line cycles in this mode, the sinusoidal components are
reduced to 0, eliminating any ripple in the energy calculation.
Therefore, total energy accumulated using the line-cycle
accumulation mode is
where nT is the accumulation time.
Note that line cycle active energy accumulation uses the same
signal path as the active energy accumulation. The LSB size of
these two methods is equivalent.
APPARENT POWER CALCULATION
Apparent power is defined as the maximum power that can be
delivered to a load. One way to obtain the apparent power is by
multiplying the voltage rms value by the current rms value:
S = VRMS × IRMS
Apparent Power Gain Calibration
The average apparent power result in each phase can be scaled
by ±100% by writing to the phase’s VAGAIN 24-bit register
IRQ pin also goes active low. The status bit is cleared and
IRQ pin is set back high by writing STATUS0 register with the
e
=
t
0
0
+
∫
t
nT
p
AVRMS
AIRMS
( )
t
dt
=
nT
k
∑
∞
=
1
V
k
I
k
Digital Signal Processor
cos
(
ϕ
k
−
AVAGAIN
γ
k
Figure 49. Apparent Power data flow and Apparent Energy Accumulation
)
Σ
Σ
VATHR[47:0]
(25)
(24)
Rev. PrC| Page 38 of 71
56 bits
where S is the apparent power and VRMS and IRMS are the rms
voltage and current, respectively. It is also called the arithmetic
apparent power.
The ADE7854 computes the arithmetic apparent power on each
phase. Figure 49 illustrates the signal processing in each phase
for the calculation of the apparent power in the ADE7854. As
VRMS and IRMS contain all harmonic information, the
apparent power computed by the ADE7854 is a total apparent
power.
The ADE7854 stores the instantaneous phase apparent powers
into AVA[23:0], BVA[23:0] and CVA[23:0] registers. Their
expression is:
where:
x=A,B,C
U, I are the rms values of the phase voltage and current.
U
the ADC inputs are at full scale.
PMAX=33,516,139 is the instantaneous power computed when
the ADC inputs are at full scale and in phase.
The xVA[23:0], x=A,B,C waveform registers may be accessed
using various serial ports. See Waveform Sampling Mode
chapter for more details.
The ADE7854 may compute the apparent power in an
alternative way by multiplying the phase rms current by an rms
voltage introduced externally. See Apparent Power Calculation
using VNOM section for details.
(AVAGAIN[23:0], BVAGAIN[23:0] or CVAG AIN[23:0]). The
VAGAIN registers are twos complement, signed registers and
have a resolution of 2
registers is expressed mathematically as
xVA
FS
,I
FS
=
are the rms values of the phase voltage and current when
U
U
FS
⋅
I
FS
I
⋅
PMAX
Preliminary Technical Data
Σ
-23
/LSB. The function of the VA gain
⋅
2
1
4
32 bit register
AVAHR[31:0]
(26)