peb2035 ETC-unknow, peb2035 Datasheet - Page 100

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

BSEL ... Bank Select
DCPY ... Disable Channel Parity Check
CPA4 ... CPA0 ... Channel Address For Parity Check
Channel Loop Back (WRITE)
LOOP
AIA ... Alarm Interrupt Acknowledge
SLB ... Enable Signaling Loop Back
DLOP ... Disable Channel Loop Back
CLA4 ... CLA0 ... Channel Address For Loop Back
Semiconductor Group
0 ... If bit CPY.SW is set, control register addresses 06 to 09 select the clear channel registers
1 ... If bit CPY.SW is set, control register addresses 01, 06 to 09 select registers EMOD and the
0 ... Normal operation.
1 ... Disables the channel parity check selected by this register. This bit should be set at least
0 ... loop back of signaling data is suppressed, e.g. a ‘clear’ channel without bitrobbing data is
1 ... channel data and signaling data will be looped back.
0 ... Normal operation.
1 ... Disables the channel loop back selected by this register. This bit should be set at least one
CCB1, CCB2, CCB3 and register ACR.
idle channel registers ICB1, ICB2, ICB3. Address 09 is reserved for future extensions.
one time-slot before changing the channel address.
CPA = 0 ... 24 selects the channel.
(NOT READABLE)
A ‘1’ written to this bit location clears the alarm interrupt signal at port AINT if the alarm
interrupt mode is enabled via bit CCR.AINT and register MASK or XC1.MCA.
Resetting this bit is not necessary.
If channel loop back is enabled by programming register LOOP
looped back.
time-slot before changing the channel address.
CLA = 1 ... 24 selects the channel.
CLA =
During loop back, the contents of the associated outgoing channel at ports XDOP, XDOM is
equal to the idle channel code programmed in register IDLE.
7
AIA
0 disables channel loop back.
SLB
DLOP
CLA4
100
CLA0
0
PEB 2035
(03)