peb2035 ETC-unknow, peb2035 Datasheet - Page 114

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

CRC Error Counter (READ)
CEC
CE7 ... CE0 ... CRC Errors
Additional Status Register (READ)
ASR
SC2 ... SC0 ... Error Simulation Counter
Semiconductor Group
–
–
Tested alarms SC2 ... SCO =
LOS
RRA (bit2 = 0)
RRA (S-bit fr. 12)
RRA (DL-pattern)
NOS (= 31 zeros)
NOS (clock check)
AIS
FEC
CVC
CEC
RPE
XPE
GPE
SLPP
SLPN
XSLP
No function if CRC6 procedure or ESF format are disabled (MODE.CRC = 0 or
GSR.FM = 2).
If ESF format and CRC6 procedure are enabled, the 8-bit counter will be incremented when
a multiframe with a CRC error has been received. A counter overflow will be inhibited.
During alarm simulation the counter will be incremented once per multiframe up to its
saturation. Disabling the counter is done by setting the bit CCR.CLR, and clearing is done
by resetting it.
As extension to this 8-bit counter, two stages (CECX.CE8, CECX.CE9) may be added to get
a 10-bit counter with a maximum value of 1023 (3FF hex). This counter mode is enabled by
setting bit RC0.ECE. All other features are the same as for 8-bit counting.
This three-bit counter is incremented by setting bit CCR.SIM. The state of the counter
determines the function to be tested:
For complete checking of the alarm indications, eight simulation steps are necessary
(ASR.SC = 0 after a complete simulation).
7
CE7
7
SC2
SC0
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RPE
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XPE
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XSLP
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CE0
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0
PEB 2035
(04)
(03)