peb2035 ETC-unknow, peb2035 Datasheet - Page 86

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

Bank Switching
After setting bit CPY.SW, control register addresses 01, 06 to 09 point to additional control
registers.
Extended Mode Register (WRITE)
Only accessible if CPY.SW = 1.
Value after RESET: 00
EMOD
DFSN … Doubleframe S
TT0X … Time-Slot 0 Extended Signaling Transparent Mode
RTM … Receive Transparent Mode
ESEI … Enable Submultiframe Error Indication Counter
Semiconductor Group
–
–
0 …Normal operation.
1 … All information of time-slot 0 at port XDI in S
No function if MODE.CRC = 0.
If MODE.CRC is set to one, the multiframing structure is determined by
EMOD.DFSN = 0: CRC-multiframe format
EMOD.DFSN = 1: Doubleframe format with internal 16-frame structure. This structure is not
transparent to the user except status flags RSP.XFLG/RFLG and multiframe begin
interrupts (see CCR.AINT, XSP.MXMB/MRMB). This new addition is implemented to
enable usage of S
doubleframe format.
assigned S
(S
Priority sequence of transparent modes: XSP.TTO > EMOD.TT0X > XSP.TT0S.
Setting this bit disconnects control of the internal speech memory from the receiver. The
speech memory is now in a ‘free running’ mode without any possibility to actualize the time
slot assignment to a probably new frame position in case of re-synchronization of the
receiver. This function can be used in conjunction with the ‘disable AIS to system interface’
feature (EMOD.DAIS) to realize undisturbed transparent reception, e.g. for applications
such as HDB3 decoder.
Only valid if CRC-multiframe format is selected.
If bit ESEI is set, counter CVC (8 or 10 bits) counts zeros in Si-bit position of frame 13 and
15 of every received CRC multiframe. There is no difference in comparison to other
counters for reading and resetting this counter and interrupt generation in case of counter
a
-bit information of registers XSW and XSP and S
7
DFSN
a
bit positions of the outgoing pulseframe. The internal information of the ACFA
H
TT0X
a
a
- Bit Stack Mode
-bit stacks RSN and XSN (MODE.ENSN) in conjunction with the“
RTM
ESEI
86
ECVE
a
-bit position (bits 4 … 8) will be inserted in
a
XFB
-bit stack XSN) will be ignored.
EDMA
DAIS
0
PEB 2035
(01)