peb2035 ETC-unknow, peb2035 Datasheet - Page 96

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

PCM 24 Mode
Register Address Arrangement
Table 15
PCM 24 Register Address Arrangement
The Control registers are normally only writeable. In a test mode they may be read by setting bit
CCR.CRD (exceptions: bits LOOP.AIA, XFDL.XMAK, XFDL.RMAK).
The status registers are only readable and are updated by the ACFA.
Semiconductor Group
Address
E,F
A
B
C
D
0
1
2
3
4
5
6
7
8
9
6
7
8
9
1
6
7
8
9
CECX
CECX
CECX
RFDL
RFDL
RFDL
Read
RSIG
RSIG
RSIG
MSR
RSR
CVC
CEC
ASR
FEC
FSR
FSR
FEC
FSR
–
–
–
–
–
MODE
EMOD
MASK
LOOP
CCB1
CCB2
CCB3
XFDL
Write
XSIG
GCR
IDLE
ICB1
ICB2
ICB3
CCR
FMR
ACR
CPY
XC0
XC1
RC0
RC1
–
–
Receive Status Register
Framing Error Counter
Code Violation Counter
CRC Error Counter
Additional Status Register
Multiframe Status Register
Framing Status Register
Receive Signaling Stack
Receive FS/DL Data
CRC Error Counter Extension
Framing Status Register
Receive Signaling Stack
Receive FS/DL Data
CRC Error Counter Extension
Framing Error Counter
Framing Status Register
Receive Signaling Stack
Receive FS/DL Data
CRC Error Counter Extension
Comment
96
Bank switching (CPY, SW = 1, CPY.BSEL = 0)
–
–
–
–
bank switching (CPY.SW = 1, CPY.BSEL = 0)
NO ACCESS ALLOWED
/ General Configuration
/ Transmit Signaling Stack
/ FS/DL Mask Register
/ Alarm Interrupt Mask
/ Idle Channel Code
/ Clear Channel Bank 1
/ Clear Channel Bank 2
/ Clear Channel Bank 3
/ Additional Control Register
/ Extended Mode Register
/ Idle Channel Bank 1
/ Idle Channel Bank 2
/ Idle Channel Bank 3
/ Mode Register
/ Channel Parity Check
/ Channel Loop Back
/ Transmit Spare Bits
/ Common Control Register
/ Receive Control 0
–
/ Transmit Control 0
/ Transmit Control 1
/ Receive Control 1
Register
PEB 2035