peb2035 ETC-unknow, peb2035 Datasheet - Page 110

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

MFBS ... Enable pure Multiframe Begin Signals
Extended Mode Register (WRITE)
Only accessible if CPY.SW = 1 and CPY.BSEL = 1.
EMOD
SSP ... Select Sync/Resync Procedure
ECVE ... Enable Code Violation Counter Extension
XFB ... Transmit Full Bauded Mode
EDMA ... Extended DMA Mode
Semiconductor Group
0 ... Specified number of errors in both FT framing and FS framing lead to loss of sync
1 ... Specified number of errors in FT framing has the sames effect as above. Specified number
0 ... Normal operation. Code violations are counted at status register CVC (8 bit length) with a
1 ... Extended code violation counting with additional counter stages (bits CECX.CV8 and
0 ... Output signals XDOP, XDOM are half bauded (normal operation).
1 ... Output signals XDOP, XDOM are full bauded.
0 ... DMA request lines RREQ and XREQ are reset at the end of the first read/write access to the
1 ... DMA request lines RREQ and XREQ remain active until the beginning of the third read/write
Only valid if ESF or F72 format is selected.
If set, signals RMFB and XMFB indicate only the multiframe begin. Additional pulses (every
12 frames) are disabled.
Only valid if F12 or F72 format is selected:
(RSR.LOS is set). In the case of FS bit framing errors, bit FSR.MLOS is set additionally. A
complete new synchronization procedure is initiated to regain pulseframe alignment and
then multiframe alignment.
of errors in FS framing only initiates a new search for multiframe alignment without
influencing pulseframe synchronous state (FSR.MLOS is set).
maximum value of 255 (‘FF’ hex).
CECX.CV9, 10 bit counter). Maximum value is 1023 (‘3FF’ hex) which is also valid for
interrupt generation if enabled.
assigned stack (rising edge of RDQ/WRQ)
access to the assigned stack. RREQ is reset with the falling edge of RDQ.XREQ is reset
with the falling edge of ACKNLQ or CEQ and remains reset if a write cycle to stack XSIG
follows. Otherwise, it becomes active again until the third access to XSIG is provided.
7
0
0
0
SSP
110
ECVE
XFB
EDMA
DAIS
0
PEB 2035
(01)