peb2035 ETC-unknow, peb2035 Datasheet - Page 90

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

CAL … CRC4 Alarm
SDI … Slip Direction Indication
Framing Error Counter (READ)
FEC
FE7 … FE0 … Framing Errors
Code Violation Counter (READ)
CVC
Semiconductor Group
0 … Negative slip: flags that the frequency of Receive Route Clock RRCLK is greater than the
1 … Positive slip: flags that the frequency of receive route clock is less than the frequency of
Not used in doubleframe format (MODE.CRC = 0 or MODE.CRC = 1 and
EMOD.DFSN = 1). In this case, set to logical ‘1’.
In CRC-multiframe mode (MODE.CRC = 1 and EMOD.DFSN = 0), this bit is set
– if force resynchronization is initiated by setting bit CCR.FRS, or
– if multiframe force resynchronization is initiated by setting bit MODE.MFCS, or
– if pulseframe alignment has been lost (RSR.LOS).
It is reset if two CRC-multiframes have been received at an interval of n
(n = 1, 2, 3 … ) without a framing error.
This bit is actualized if the receive slip indication (RSR.SLP) toggles:
frequency of internal system clock
internal system clock
This 8-bit counter will be incremented when a FAS word has been received with an error.
Framing errors will not be counted during asynchronous state. A counter overflow will be
inhibited. During alarm simulation, the counter is incremented every 250 s up to its
saturation. Disabling the counter is done by setting bit CCR.CLR; clearing is done by
resetting it.
7
7
CV7
FE7
a frame will be repeated.
a frame will be skipped.
90
CV0
FE0
0
0
2 ms
PEB 2035
(01)
(02)