peb2035 ETC-unknow, peb2035 Datasheet - Page 117

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

FEH5 ... FEH0 ... F-Bit Error History
Note: All error history bits corresponding to FS bits substituted by data link information are fixed
Receive Signaling Stack (READ)
RSIG
RS7 ... RS0 ... Receive Signaling Data
Semiconductor Group
to‘0’.
The bits are set if errors occur in the corresponding framing bit locations. They will be
updated once per superframe (ESF format) or every six frames (other framing formats).
Organization:
ESF
FEH5: FAS (24)
FEH4: FAS (20)
FEH3: FAS (16)
FEH2: FAS (12)
FEH1: FAS (8)
FEH0: FAS (4)
If the use of the internal signaling register is enabled via bit XC0.ISIG three bytes of received
signaling data will be stored in this stack. A DMA or interrupt request at port RREQ requires
reading the stack three times. Access to this stack is possible
– via a normal read cycle to the chip address location plus stack address (07 Hex), or
– via a direct read access with the signal at port ACKNLQ as access enable in a read cycle
I/O to memory DMA transfer.
In CCS or CAS-CC mode three bytes of signaling data of channels 17 or 24 (depending on
MODE.CTM and FMR.SM24) are stored in this stack. The MSB of the first byte read from
the stack is received first.
In CAS-BR mode every eighth bit per channel of the signaling frame is stored:
RS7: receive channel 1, 9, 17
RS6: receive channel 2, 10, 18
RS5: receive channel 3, 11, 19
RS4: receive channel 4, 12, 20
RS3: receive channel 5, 13, 21
RS2: receive channel 6, 14, 22
RS1: receive channel 7, 15, 23
RS0: receive channel 8, 16, 24
without the need of generating the chip enable signal at port CEQ. This feature is useful for
7
RS7
others
FT (2 or 8)
FT (6 or 12)
FT (5 or 11)
FT (4 or 10)
FT (3 or 9)
FT (1 or 7)
117
RS0
0
PEB 2035
(07)