peb2035 ETC-unknow, peb2035 Datasheet - Page 108

• Manufacturer Part Number: peb2035
• Description: Communications Advanced Cmos Frame Aligner
• Manufacturer: ETC-unknow

Alarm Interrupt Mask Register (WRITE)
MASK
MLOS ... Mask: Loss Of Synchronization
MAIS ... Mask: Alarm Indication Signal
MNOS ... Mask: No Signal
MRRA ... Mask: Receive Remote Alarm
MSLP ... Mask: Receive Slip Indication
MCEC ... Mask: CRC Error Counter Overflow
MFEC ... Mask: Framing Error Counter Overflow
MCVC ... Mask: Code Violation Counter Overflow
Idle Channel Code Register (WRITE)
IDLE
IDL7 ... IDL0 ... Idle Channel Code
Bank Switching
After setting bit CPY.SW control register addresses 01, 06 to 09 select additional control registers
in dependance of bit CPY.BSEL.
Semiconductor Group
If the alarm interrupt mode is enabled via bit CCR.AINT this mask register selects the alarm
sources:
Mask bit = 0: alarm source disabled.
Mask bit = 1: alarm source enabled.
Selected alarms cause an interrupt signal at port AINT. Acknowledging is done by writing
a ‘1’ to the bit LOOP.AIA. Triggering a new interrupt by the same source is possible only
after this source has been inactive.
If channel loop back is enabled by programming the register LOOP, the contents of the
assigned outgoing channel at ports XDOP, XDOM is set equal to the idle channel code
selected by this register.
Additionally, the specified pattern overwrites the contents of all channels of the outgoing
PCM frame selected via the idle channel register bank ICB1 ... ICB3.
Its initial value (FF Hex after switching to PCM 24 mode) may be overwritten via the
microprocessor interface.
7
7
IDL7
MLOS
MAIS
MNOS MRRA MSLP MCEC MFEC MCVC
108
IDL0
0
0
PEB 2035
(0C)
(0D)