n25q032 Numonyx, n25q032 Datasheet - Page 33

• Manufacturer Part Number: n25q032
• Description: 32-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

6.1
6.1.1
6.1.2
6.1.3
6.1.4
Legacy SPI Status Register
The Status Register contains a number of status and control bits that can be read or set by
specific instructions: Read Status Register (RDSR) and Write Status Register (WRSR). This
is available in all the 3 protocols (Extended SPI, DIO-SPI, and QIO-SPI).
Table 2.
WIP bit
The Write In Progress (WIP) bit set to 1 indicates that the memory is busy with a Write
Status Register, Program or Erase cycle. 0 indicates no cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit set to 1 indicates that the internal Write Enable Latch is
set. When set to 0 the internal Write Enable Latch is reset and no Write Status Register,
Program or Erase instruction is accepted.
Block Protect bits (BP2, BP1, BP0)
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area, as defined in
sizes, Upper (TB bit = 0)
Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected
mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block
Protect (BP2, BP1, BP0) bits are 0.
TB bit
The Top/Bottom (TB) bit is non-volatile. It can be set and reset with the Write Status Register
(WRSR) instruction provided that the Write Enable (WREN) instruction has been issued.
Status register write protect
SRWD
b7
Status register format
0
becomes protected against all program and erase instructions. The
Top/bottom bit
TB
BP2
Block protect bits
BP1
Write enable latch bit
BP0
Table 10.: Protected area
WEL
Write in progress bit
WIP
b0
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