n25q032 Numonyx, n25q032 Datasheet - Page 85

• Manufacturer Part Number: n25q032
• Description: 32-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

9.1.26
S
C
DQ0
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes (pointing to any address in the
targeted sector and one data byte on Serial Data input (DQ0). The instruction sequence is
shown in Figure 22. Chip Select (S) must be driven High after the eighth bit of the data byte
has been latched in, otherwise the Write to Lock Register (WRLR) instruction is not
executed.
Lock Register bits are volatile, and therefore do not require time to be written. When the
Write to Lock Register (WRLR) instruction has been successfully executed, the Write
Enable Latch (WEL) bit is reset after a delay time less than tSHSL minimum value.
Any Write to Lock Register (WRLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 34. Write to Lock Register instruction sequence
*Address bits A23 and A22 are “Don’t Care.”
Table 20.
1. Values of (b1, b0) after power-up are defined in
All sectors
0
1
Sector
2
Instruction
Lock Register in
3
4
5
6
7
b7-b2
Bit
MS B
b1
b0
23
8
(1)
22 21
9 10
*24-Bit Address
Sector Lock Down bit value (refer to
Sector Write Lock bit value (refer to
3
28 29 30 31 32 33 34 35
Section 7: Protection
2
1
0
MS B
7
6
Lock R egister
5
modes.
Value
4
‘0’
In
3
36 37 38
Table
2
Table
1
19)
19)
0
39
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