n25q032 Numonyx, n25q032 Datasheet - Page 40

• Manufacturer Part Number: n25q032
• Description: 32-mbit 3 V, Multiple I/o, 4-kbyte Subsector Erase, Xip Enabled, Serial Flash Memory With 108 Mhz Spi Bus Interface
• Manufacturer: Numonyx

6.4
Table 7.
6.4.1
40/160
VECR<7>
VECR<6>
VECR<5>
VECR<4>
VECR<3>
VECR<2:0>
Bit
Volatile Enhanced Configuration Register
The Volatile Enhanced Configuration Register (VECR) affects the memory configuration
after every execution of Write Volatile Enhanced Configuration Register (WRVECR)
instruction: this instruction overwrite the memory configuration set during the POR
sequence by the Non Volatile Configuration Register (NVCR). Its purpose is:
Volatile Enhanced Configuration Register
Quad Input Command VECR<7>
The Quad Input Command configuration bit can be used to make the memory start working
in QIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register
Quad Input
Command
Dual Input
Command
Reserved
Reset/Hold
disable
Accelerator
pin enable in
QIO-SPI
protocol or in
QIFP/QIEFP
Output Driver
Strength
enabling of QIO-SPI protocol and DIO-SPI protocol
HOLD (Reset) functionality disabling
To enable the VPP functionality in Quad I/O modify operations
To define output driver strength (3 bit)
Parameter
Warning:
0
1
0
1
x
0
1
0
1
000
001
010
011
100
101
110
111
WARNING: in case of both QIO-SPI and DIO-SPI enabled, the
memory works in QIO-SPI
Value
Enabled
Disabled (default)
Enabled
Disabled (default)
Reserved
Disabled
Enabled (default)
Enabled
Disabled (default)
reserved
90
60
45
reserved
20
15
30 (default)
Description
Fixed value = 0b
Enable command on four input lines
Enable command on two input lines
Disable Pad Hold/Reset functionality
The bit must be considered in case of QIFP,
QIEFP, or QIO-SPI protocol. It is “Don’t
Care” otherwise.
Impedance at V
CC
/2
Note