atmega32u4-16mu ATMEL Corporation, atmega32u4-16mu Datasheet - Page 147

• Manufacturer Part Number: atmega32u4-16mu
• Description: Atmega32u4 8-bit Avr Microcontroller With 32k Bytes Of Isp Flash And Usb Controller
• Manufacturer: ATMEL Corporation

15.7
7766A–AVR–03/08
Timer/Counter Timing Diagrams
output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when
WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (See
value will only be visible on the port pin if the data direction for the port pin is set as output. The
PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match
between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x
Register at compare match between OCR2x and TCNT2 when the counter decrements. The
PWM frequency for the output when using phase correct PWM can be calculated by the follow-
ing equation:
The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-
TOM. There are two cases that give a transition without Compare Match.
On the following figures the timer clock (clk
include information on when Interrupt Flags are set.
Timer/Counter operation. The figure shows the count sequence close to the MAX value in all
modes other than phase correct PWM mode.
Figure 15-8. Timer/Counter Timing Diagram, no Prescaling
• OCR2A changes its value from MAX, like in
• The timer starts counting from a value higher than the one in OCR2A, and for that reason
OCn pin value is the same as the result of a down-counting compare match. To ensure
symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-
counting Compare Match.
misses the Compare Match and hence the OCn change that would have happened on the
way up.
TCNTn
(clk
TOVn
clk
clk
I/O
I/O
Tn
/1)
MAX - 1
Figure 15-7
f
OCnxPCPWM
MAX
OCnx has a transition from high to low even though
T2
) is shown as a clock enable signal. The figures
Figure
=
Table 15-3 on page
----------------- -
N 510
f
clk_I/O
Figure 15-8
15-7. When the OCR2A value is MAX the
⋅
BOTTOM
contains timing data for basic
ATmega32U4
150). The actual OC2x
BOTTOM + 1
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