atmega32u4-16mu ATMEL Corporation, atmega32u4-16mu Datasheet - Page 240

• Manufacturer Part Number: atmega32u4-16mu
• Description: Atmega32u4 8-bit Avr Microcontroller With 32k Bytes Of Isp Flash And Usb Controller
• Manufacturer: ATMEL Corporation

20.6.5
20.7
240
AVR USART MSPIM vs. AVR SPI
ATmega32U4
USART MSPIM Baud Rate Registers - UBRRnL and UBRRnH
These bits select the mode of operation of the USART as shown in
Control and Status Register n C – UCSRnC” on page 226
USART operation. The MSPIM is enabled when both UMSELn bits are set to one. The
UDORDn, UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM is
enabled.
Table 20-3.
• Bit 5:3 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnC is written.
• Bit 2 - UDORDn: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the
data word is transmitted first. Refer to the Frame Formats section page 4 for details.
• Bit 1 - UCPHAn: Clock Phase
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last)
edge of XCKn. Refer to the SPI Data Modes and Timing section page 4 for details.
• Bit 0 - UCPOLn: Clock Polarity
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and
UCPHAn bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and
Timing section page 4 for details.
The function and bit description of the baud rate registers in MSPI mode is identical to normal
USART operation. See “USART Baud Rate Registers – UBRRLn and UBRRHn” on page 228.
The USART in MSPIM mode is fully compatible with the AVR SPI regarding:
However, since the USART in MSPIM mode reuses the USART resources, the use of the
USART in MSPIM mode is somewhat different compared to the SPI. In addition to differences of
the control register bits, and that only master operation is supported by the USART in MSPIM
mode, the following features differ between the two modules:
UMSELn1
0
0
1
1
• Master mode timing diagram.
• The UCPOLn bit functionality is identical to the SPI CPOL bit.
• The UCPHAn bit functionality is identical to the SPI CPHA bit.
• The UDORDn bit functionality is identical to the SPI DORD bit.
• The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI has no
buffer.
UMSELn Bits Settings
1
0
1
UMSELn0
0
Mode
Asynchronous USART
(Reserved)
Master SPI (MSPIM)
Synchronous USART
for full description of the normal
Table
20-3. See
7766A–AVR–03/08
“USART