atmega32u4-16mu ATMEL Corporation, atmega32u4-16mu Datasheet - Page 36

• Manufacturer Part Number: atmega32u4-16mu
• Description: Atmega32u4 8-bit Avr Microcontroller With 32k Bytes Of Isp Flash And Usb Controller
• Manufacturer: ATMEL Corporation

6.7
6.8
6.8.1
36
Clock Output Buffer
System Clock Prescaler
ATmega32U4
Clock Prescaler Register – CLKPR
These bits are reserved and will always read as zero.
• Bit 1 – RCON: RC Oscillator On
This bit is set by hardware to one if the RC Oscillator is running.
This bit is set by hardware to zero if the RC Oscillator is stopped.
• Bit 0 – EXTON: External Clock / Low Power Crystal Oscillator On
This bit is set by hardware to one if the External Clock / Low Power Crystal Oscillator is running.
This bit is set by hardware to zero if the External Clock / Low Power Crystal Oscillator is
stopped.
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-
cuits on the system. The clock also will be output during reset, and the normal operation of I/O
pin will be overridden when the fuse is programmed. Any clock source, including the internal RC
Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is
used, it is the divided system clock that is output .
The AVR USB has a system clock prescaler, and the system clock can be divided by setting the
“Clock Prescaler Register – CLKPR” on page
tem clock frequency and the power consumption when the requirement for processing power is
low. This can be used with all clock source options, and it will affect the clock frequency of the
CPU and all synchronous peripherals. clk
as shown in
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the
state of the prescaler - even if it were readable, and the exact time it takes to switch from one
clock division to the other cannot be exactly predicted. From the time the CLKPS values are writ-
ten, it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this
interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the
period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
Bit
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
CLKPR to zero.
Table
7
6-10.
6
5
4
I/O
, clk
36. This feature can be used to decrease the sys-
3
ADC
, clk
2
CPU
, and clk
1
FLASH
0
are divided by a factor
7766A–AVR–03/08