atmega32u4-16mu ATMEL Corporation, atmega32u4-16mu Datasheet - Page 168

• Manufacturer Part Number: atmega32u4-16mu
• Description: Atmega32u4 8-bit Avr Microcontroller With 32k Bytes Of Isp Flash And Usb Controller
• Manufacturer: ATMEL Corporation

16.7
16.8
16.8.1
168
Synchronous update
Modes of Operation
ATmega32U4
Normal Mode
To avoid unasynchronous and incoherent values in a cycle, if a synchronous update of one of
several values is necessary, all values can be updated at the same time at the end of the PWM
cycle by the Timer controller. The new set of values is calculated by software and the effective
update can be initiated by software.
Figure 16-11. Lock feature and Synchronous update
In normal operation, each write to a Compare register is effective at the end of the current cycle.
But some cases require that two or more Compare registers are updated synchronously, and
that may not be always possible, mostly at high speed PWM frequencies. That may result in
some PWM periods with incoherent values.
When using the Lock feature (TLOCK4=1), the values written to the Compare registers are not
effective and temporarily buffered. When releasing the TLOCK4 bit, the update is initiated and
the new whole set of values will be loaded at the end of the current PWM cycle.
See
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the combination of the Waveform Generation mode (bits PWM4x and WGM40) and
Compare Output mode (COM4x1:0) bits. The Compare Output mode bits do not affect the
counting sequence, while the Waveform Generation mode bits do. The COM4x1:0 bits control
whether the PWM output generated should be inverted, non-inverted or complementary. For
non-PWM modes the COM4x1:0 bits control whether the output should be set, cleared, or tog-
gled at a Compare Match.
The simplest mode of operation is the Normal mode (PWM4x = 0), the counter counts from
BOTTOM to TOP (defined as OCR4C) then restarts from BOTTOM. The OCR4C defines the
TOP value for the counter, hence also its resolution, and allows control of the Compare Match
output frequency. In toggle Compare Output Mode the Waveform Output (OCW4x) is toggled at
Compare Match between TCNT4 and OCR4x. In non-inverting Compare Output Mode the
Cycle with
Set i
– Setting OCR4A = 0x85 (= b’10000101’) signifies that the true value of “Compare A”
Regulation Loop
Calculation
Section 16.12.5 ”TCCR4E – Timer/Counter4 Control Register E” on page
register is 0x42 (b’01000010’) and that the Enhanced bit is set. That means that the
duty cycle obtained (51.95%) will be the intermediate value between duty cycles that
can be obtained by 0x42 and 0x43 Compare values (51.56%, 52.34%).
Cycle with
Set i
TLOCK4=1
Writing to Timer
Registers Set j
Cycle with
Set i
TLOCK4=0
Cycle with
Set i
Request for an
Update
Cycle with
Set j
188.
7766A–AVR–03/08