at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 104

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

19.4
19.5
19.5.1
104
Arbitration
Arbitration Rules
AT91CAP7E
Undefined Length Burst Arbitration
The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases
occur, i.e. when two or more masters try to access the same slave at the same time. One arbiter
per AHB slave is provided, thus arbitrating each slave differently.
The Bus Matrix provides the user with the possibility of choosing between 2 arbitration types for
each slave:
This choice is made via the field ARBT of the Slave Configuration Registers (MATRIX_SCFG).
Each algorithm may be complemented by selecting a default master configuration for each
slave.
When a re-arbitration must be done, specific conditions apply. See
Rules” on page
Each arbiter has the ability to arbitrate between two or more different master requests. In order
to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitra-
tion may only take place during the following cycles:
In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix pro-
vides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end
of burst is used as a defined length burst transfer and can be selected from among the following
five possibilities:
This selection can be done through the field ULBT of the Master Configuration Registers
(MATRIX_MCFG).
1. Round-Robin Arbitration (default)
2. Fixed Priority Arbitration
1. Idle Cycles: When a slave is not connected to any master or is connected to a master
2. Single Cycles: When a slave is currently doing a single access.
3. End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For
4. Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that
1. Infinite: No predicted end of burst is generated and therefore INCR burst transfer will
2. One beat bursts: Predicted end of burst is generated at each single transfer inside the
3. Four beat bursts: Predicted end of burst is generated at the end of each four beat
4. Eight beat bursts: Predicted end of burst is generated at the end of each eight beat
5. Sixteen beat bursts: Predicted end of burst is generated at the end of each sixteen beat
which is not currently accessing it.
defined length burst, predicted end of burst matches the size of the transfer but is man-
aged differently for undefined length burst.
page 104.
the current master access is too long and must be broken.
tration” on page 105.
never be broken.
INCP transfer.
boundary inside INCR transfer.
boundary inside INCR transfer.
boundary inside INCR transfer.
104.
See “Undefined Length Burst Arbitration” on
See “Slot Cycle Limit Arbi-
Section 19.5 ”Arbitration
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