at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 179

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

Figure 22-3. Read Burst, 32-bit SDRAM Access
22.6.3
8549A–CAP–10/08
Border Management
SDRAMC_A[12:0]
D[31:0]
SDCS
SDWE
(Input)
SDCK
RAS
CAS
When the memory row boundary has been reached, an automatic page break is inserted. In this
case, the SDRAM controller generates a precharge command, activates the new row and initi-
ates a read or write command. To comply with SDRAM timing parameters, an additional clock
cycle is inserted between the precharge/active (t
mand. This is described in
Row n
t
RCD
= 3
col a
Figure 22-4
CAS = 2
col b
Dna
below.
col c
Dnb
col d
RP
) command and the active/read (t
Dnc
col e
Dnd
col f
Dne
AT91CAP7E
Dnf
RCD
) com-
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