at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 61

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at91cap7e

Manufacturer Part Number
at91cap7e
Description
Customizable Microcontroller
Manufacturer
ATMEL Corporation
Datasheet

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13. CAP7E Debug and Test
13.1
13.2
Figure 13-1. Debug and Test Block Diagram
8549A–CAP–10/08
Overview
Block Diagram
TAP: Test Access Port
ARM7TDMI
The AT91CAP7E features a number of complementary debug and test capabilities. A common
JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as down-
loading code and single-stepping through programs. The Debug Unit provides a two-pin UART
that can be used to upload an application into internal SRAM. It manages the interrupt handling
of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communica-
tion Channel.
A set of dedicated debug and test input/output pins gives direct access to these capabilities from
a PC-based test environment.
Boundary
Port
ICE
DBGU
ICE/JTAG
TAP
Reset
Test
and
POR
TMS
TCK
TDI
JTAGSEL
TDO
DTXD
DRXD
RTCK
TST
NTRST
AT91CAP7E
61

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