at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 43

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

11.3.1
Figure 11-2. FPGA Interface architecture
11.3.2
8549A–CAP–10/08
CAP7E
Internal
CAP7E
AHB
Interface Modules
Serializer Modules
D
P
C
ZBT Interface
Masters A-B
Slaves A-B
Slaves C-D
APB’s
Q
R
‘s
I
S0
NOTE
Each serializer block on CAP7E and FPGA includes a FSM (Finite State Machine) that can
communicate with the AHB bus. Thus, the interface can handle simultaneous transfers from
either side eliminating the common bottleneck found using other interface types such as EBI
or PIO.
By using the dedicated DMA channels (PDC), the overall system performance and band-
width is greatly improved. The ARM7TDMI need not be burdened with transferring data to or
from the FPGA but can be reserved for more intense processing.
Figure 11-2
The Serializer Module handles all the AHB and serial communications. It contains 2 main
sub-modules, a finite state machine (FSM) and a shifter.
•
FSM: This block communicates with the AHB bus. When a master initiates a transfer
(read/write operation), the FSM inserts any necessary wait states using HREADY to
comply with the AHB protocol. The number of wait cycles inserted by the FSM depends
upon the two ratios between the CAP7E and FPGA AHB clocks and the FPGA Interface
Serial Clock (FPIF_SCLK). Therefore, the smaller those ratios, the less number of wait
states are inserted.
S0
S1
S0
S1
S0
S0
S1
The AHB master clock on the CAP7E is independent from the AHB clock on the
FPGA. Therefore, the FPGA can run at a different frequency than the CAP7E.
shows a top level description for both interfaces (CAP7E and FPGA).
FPIF Serial Clock
modes
FPIF Reset
FPGA
CAP7E Ctrl
S0
S0
S1
S0
S1
S0
S1
S0
PDC Channels
ZBT Interface
Masters A-B
Slaves C-D
Slaves A-B
PDC
FPGA
Internal
AHB
APB’s
AT91CAP7E
IRQ
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