at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 366

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

29.6.3.12
Figure 29-25. Framing Error Status
29.6.3.13
366
AT91CAP7E
Framing Error
Transmit Break
Baud Rate
Table 29-8.
The receiver is capable of detecting framing errors. A framing error happens when the stop bit of
a received character is detected at level 0. This can occur if the receiver and the transmitter are
fully desynchronized.
A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The
FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is
cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1.
The user can request the transmitter to generate a break condition on the TXD line. A break con-
dition drives the TXD line low during at least one complete character. It appears the same as a
0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the
TXD line at least during one character until the user requests the break condition to be removed.
A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This
can be performed at any time, either while the transmitter is empty (no character in either the
Shift Register or in US_THR) or when a character is being transmitted. If a break is requested
while a character is being shifted out, the character is first completed before the TXD line is held
low.
Once STTBRK command is requested further STTBRK commands are ignored until the end of
the break is completed.
The break condition is removed by writing US_CR with the STPBRK bit at 1. If the STPBRK is
requested before the end of the minimum break duration (one character, including start, data,
parity and stop bits), the transmitter ensures that the break condition completes.
FRAME
US_CR
RXRDY
Clock
Write
RXD
Baud Rate
200000
56000
57600
Start
Bit
Maximum Time-out Period (Continued)
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit Time
Bit
Stop
18
17
Bit
5
RSTSTA = 1
Time-out
1 170
1 138
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