at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 45

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

Figure 11-4. Dual Master Mode
11.3.4
Figure 11-5. Read/Write timing for Single Master Mode
8549A–CAP–10/08
CAP7E
AHB
FPIF_SCLK
HWDATA
Transfer Timing
HRDATA
HREADY
HADDR
CAP7E AHB CLK
Ctrl
A
C
S0
S1
t1
CAP7E FSM
D
Shifter
As mentioned previously, the number of clocks per transfer and therefore the effective trans-
fer speed depends upon the two ratios between the CAP7E and FPGA AHB clock frequen-
cies and the FPIF_SCLK. In addition, the Master Mode selection affects the effective transfer
speed as follows:
•
•
Figure 11-5
•
•
Single Master Mode: Takes 4 FPIF_SCLK cycles to transfer data for 1 AHB interface.
See t2 and t3 on
Dual Master Mode: Takes 8 FPIF_SCLK cycles to transfer all AHB data of 2 AHB
interfaces.
t1: Time for a standard 2 cycles AHB
t2: Time to transfer the request to FPGA (4 cycles single AHB interface, 8 cycles dual
AHB interface).
Serial Data to FPGA
shows all the timing for a transfer between the CAP7E and the FPGA.
t2
FPIF Serial Clock
Control
Figure 11-5
S0
S1
t6
t3
Serial Data to CAP7E
below.
t4
FPGA FSM
Shifter
FPGA AHB CLK
Response
t5
D
S0
S1
FPGA
AT91CAP7E
AHB
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