at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 340

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

28.7.9
Name:
Access Type:
• CPOL: Clock Polarity
0 = The inactive state value of SPCK is logic level zero.
1 = The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the
required clock/data relationship between master and slave devices.
• NCPHA: Clock Phase
0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is
used with CPOL to produce the required clock/data relationship between master and slave devices.
• CSAAT: Chip Select Active After Transfer
0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is
requested on a different chip select.
• BITS: Bits Per Transfer
The BITS field determines the number of data bits transferred. Reserved values should not be used.
340
31
23
15
7
AT91CAP7E
SPI Chip Select Register
30
22
14
6
BITS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
BITS
29
21
13
5
SPI_CSR0... SPI_CSR3
Read/Write
28
20
12
4
DLYBCT
DLYBS
SCBR
CSAAT
27
19
11
3
Bits Per Transfer
26
18
10
2
–
Reserved
10
11
12
13
14
15
16
8
9
NCPHA
25
17
9
1
8549A–CAP–10/08
CPOL
24
16
8
0