at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 64

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

13.5
13.5.1
13.5.2
13.5.3
13.5.4
64
Functional Description
AT91CAP7E
Test Pin
Embedded In-circuit Emulator
Debug Unit
IEEE 1149.1 JTAG Boundary Scan
One dedicated pin, TST, is used to define the device operating mode. The user must make sure
that this pin is tied at low level to ensure normal operating conditions. Other values associated
with this pin are reserved for manufacturing test.
The ARM7TDMI Embedded ICE is supported via the ICE/JTAG port. The internal state of the
ARM7TDMI is examined through an ICE/JTAG port.
The ARM7TDMI processor contains hardware extensions for advanced debugging features: • In
halt mode, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the
contents of the ARM7TDMI registers. This data can be serially shifted out without affecting the
rest of the system. • In monitor mode, the JTAG interface is used to transfer data between the
debugger and a simple monitor program running on the ARM7TDMI processor.
There are three scan chains inside the ARM7TDMI processor which support testing, debugging,
and programming of the Embedded ICE. The scan chains are controlled by the ICE/JTAG port.
Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly
between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed.
For further details on the Embedded In-Circuit-Emulator, see the ARM document: ARM7TDMI
(Rev 4) Technical Reference Manual (DDI0210B).
The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several
debug and trace purposes and offers an ideal means for in-situ programming solutions and
debug monitor communication. Moreover, the association with two Peripheral DMA Controller
channels permits packet handling of these tasks with processor time reduced to a minimum.
The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals
that come from the ICE and that trace the activity of the Debug Communication Channel.The
Debug Unit allows blockage of access to the system through the ICE interface.
A specific register, the Debug Unit Chip ID Register (DBGU_CIDR), gives information about the
product’s internal configuration and its version.
The AT91CAP7E Debug Unit Chip ID value is 0x8377 09xx on 32-bit width (1000 0011 0111
0111 0000 1001 010x xxxx). The last five bits of the register are reserved for a version number.
For further details on the Debug Unit, see the Debug Unit section.
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging
technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST
and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds
with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1
JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be per-
formed after JTAGSEL is changed.
8549A–CAP–10/08