at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 72

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

Figure 14-6. Software Reset
14.3.3.5
72
AT91CAP7E
Watchdog Reset
SRCMP in RSTC_SR
Write RSTC_CR
If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field
ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset.
If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field
RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in
RSTTYP.
As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Prog-
ress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left.
No other software reset can be performed while the SRCMP bit is set, and writing any value in
RSTC_CR has no effect.
if PROCRST=1
The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 2 Slow Clock
cycles.
When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in
WDT_MR:
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a
processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog
Reset, and the Watchdog is enabled by default and with a period set to a maximum.
When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset
controller.
periph_nreset
if PERRST=1
if EXTRST=1
• If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST
• If WDRPROC = 1, only the processor reset is asserted.
proc_nreset
(nrst_out)
line is also asserted, depending on the programming of the field ERSTL. However, the
resulting low level on NRST does not result in a User Reset state.
RSTTYP
NRST
SLCK
MCK
Freq.
Any
Any
Resynch.
1 cycle
Processor Startup
XXX
= 3 cycles
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
0x3 = Software Reset
8549A–CAP–10/08