at32uc3b0512-z2ues ATMEL Corporation, at32uc3b0512-z2ues Datasheet - Page 288
at32uc3b0512-z2ues
Manufacturer Part Number
at32uc3b0512-z2ues
Description
32-bit Avr Microcontroller
Manufacturer
ATMEL Corporation
Datasheet
1.AT32UC3B0512-Z2UES.pdf
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• DATNB: Data Number per Frame
• MSBF: Most Significant Bit First
• DATDEF: Data Default Value
• DATLEN: Data Length
32059J–12/2010
DATLEN
Others
8-15
Note: The four most significant bits for this field are located in the FSLENHI field.
The pulse length is equal to ({FSLENHI,FSLEN} + 1) transmit clock periods, i.e., the pulse length can range from 1 to 256
transmit clock periods. If {FSLENHI,FSLEN} is zero, the Transmit Frame Sync signal is generated during one transmit clock
period.
This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB + 1).
1: The most significant bit of the data register is shifted out first in the bit stream.
0: The lowest significant bit of the data register is shifted out first in the bit stream.
This bit defines the level driven on the TX_DATA pin while out of transmission.
Note that if the pin is defined as multi-drive by the I/O Controller, the pin is enabled only if the TX_DATA output is one.
1: The level driven on the TX_DATA pin while out of transmission is one.
0: The level driven on the TX_DATA pin while out of transmission is zero.
The bit stream contains (DATLEN + 1) data bits.
This field also defines the transfer size performed by the Peripheral DMA Controller assigned to the transmitter.
1-7
0
Transfer Size
Forbidden value (1-bit data length is not supported)
Data transfer are in bytes
Data transfer are in halfwords
Data transfer are in words
AT32UC3B
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