at32uc3b0512-z2ues ATMEL Corporation, at32uc3b0512-z2ues Datasheet - Page 387

• Manufacturer Part Number: at32uc3b0512-z2ues
• Description: 32-bit Avr Microcontroller
• Manufacturer: ATMEL Corporation

22.7.2.12
32059J–12/2010
Management of IN endpoints
•Overview
TXINI
FIFOCON
IN packets are sent by the USB device controller upon IN requests from the host. All the data
can be written which acknowledges or not the bank when it is full.
The endpoint must be configured first.
The TXINI bit is set at the same time as FIFOCON when the current bank is free. This triggers
an EPnINT interrupt if the Transmitted IN Data Interrupt Enable (TXINE) bit in UECONn is one.
TXINI shall be cleared by software (by writing a one to the Transmitted IN Data Interrupt Enable
Clear bit in the Endpoint n Control Clear register (UECONnCLR.TXINIC)) to acknowledge the
interrupt, what has no effect on the endpoint FIFO.
The user then writes into the FIFO (see
DATA)” on page
UECONnCLR to clear the FIFOCON bit. This allows the USBB to send the data. If the IN end-
point is composed of multiple banks, this also switches to the next bank. The TXINI and
FIFOCON bits are updated in accordance with the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
The RWALL bit is set when the current bank is not full, i.e. the software can write further data
into the FIFO.
Figure 22-17. Example of an IN Endpoint with 1 Data Bank
SW
write data to CPU
NAK
BANK 0
483) and write a one to the FIFO Control Clear (FIFOCONC) bit in
SW
IN
”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-
(bank 0)
DATA
HW
ACK
SW
write data to CPU
BANK 0
AT32UC3B
SW
IN
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