at32uc3b0512-z2ues ATMEL Corporation, at32uc3b0512-z2ues Datasheet - Page 530

• Manufacturer Part Number: at32uc3b0512-z2ues
• Description: 32-bit Avr Microcontroller
• Manufacturer: ATMEL Corporation

32059J–12/2010
• the waveform period. This channel parameter is defined in the CPRD field of the CPRDx
• the waveform duty cycle. This channel parameter is defined in the CDTY field of the CDTYx
• the waveform polarity. At the beginning of the period, the signal can be at high or low level.
• the waveform alignment. The output waveform can be left or center aligned. Center aligned
register.
- If the waveform is left aligned, then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (CLK_PWM) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (CLK_PWM) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
This property is defined in the CPOL field of the CMRx register. By default the signal starts by
a low level.
waveforms can be used to generate non overlapped waveforms. This property is defined in the
CALG field of the CMRx register. The default mode is left aligned.
(
------------------------------ -
(
----------------------------------------- -
(
---------------------------------------- -
(
--------------------------------------------------- -
CLK_PWM
X CPRD
CRPD
2
2
CLK_PWM
duty cycle
CLK_PWM
×
×
×
duty cycle
CLK_PWM
X CPRD
CPRD DIVA
×
×
DIVA
)
×
=
)
)
=
or
(
------------------------------------------------------------------------------------------------------- -
period 1 fchannel_x_clock
(
---------------------------------------------------------------------------------------------------------------------- -
)
(
period 2 ⁄
(
--------------------------------------------- -
or
CRPD
CLK_PWM
(
--------------------------------------------------- -
2 CPRD
–
×
×
CLK_PWM
DIVAB
⁄
) 1 fchannel_x_clock
–
×
period
⁄
(
)
DIVB
period 2 ⁄
)
)
×
CDTY
×
CDTY
)
) )
AT32UC3B
530