at32uc3b0512-z2ues ATMEL Corporation, at32uc3b0512-z2ues Datasheet - Page 528
at32uc3b0512-z2ues
Manufacturer Part Number
at32uc3b0512-z2ues
Description
32-bit Avr Microcontroller
Manufacturer
ATMEL Corporation
Datasheet
1.AT32UC3B0512-Z2UES.pdf
(680 pages)
- Current page: 528 of 680
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24.6
24.6.1
32059J–12/2010
Functional Description
PWM Clock Generator
The PWM macrocell is primarily composed of a clock generator module and
Figure 24-2. Functional View of the Clock Generator Block Diagram
Caution: Before using the PWM macrocell, the programmer must ensure that the PWM clock in
the Power Manager is enabled.
The PWM macrocell master clock, CLK_PWM, is divided in the clock generator module to pro-
vide different clocks available for all channels. Each channel can independently select one of the
– Clocked by the system clock, CLK_PWM, the clock generator module provides 13
– Each channel can independently choose one of the clock generator outputs.
– Each channel generates an output waveform with attributes that can be defined
clocks.
independently for each channel through the user interface registers.
CLK_PWM
modulo n
Counter
PREA
PREB
MR
MR
Divider A
Divider B
DIVA
DIVB
CLK_PWM/32
CLK_PWM/2
CLK_PWM/16
CLK_PWM/64
CLK_PWM/128
CLK_PWM/256
CLK_PWM/512
CLK_PWM/1024
CLK_PWM
CLK_PWM/4
CLK_PWM/8
clk B
clk A
AT32UC3B
7
channels.
528
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