mc9s08dz32amlfr Freescale Semiconductor, Inc, mc9s08dz32amlfr Datasheet - Page 140

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mc9s08dz32amlfr

Manufacturer Part Number
mc9s08dz32amlfr
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Chapter 6 Parallel Input/Output Control
6.5.11.3
6.5.11.4
Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
140
PTLPE[7:0]
PTLSE[7:0]
Reset:
Reset:
Field
Field
7:0
7:0
rate control to the desired value to ensure correct operation.
W
W
R
R
PTLPE7
PTLSE7
Internal Pull Enable for Port L Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTL pin. For port L pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port L bit n.
1 Internal pull-up device enabled for port L bit n.
Output Slew Rate Enable for Port L Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTL pin. For port L pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port L bit n.
1 Output slew rate control enabled for port L bit n.
Port L Pull Enable Register (PTLPE)
0
Port L Slew Rate Enable Register (PTLSE)
0
7
7
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.
PTLPE6
PTLSE6
Figure 6-67. Internal Pull Enable for Port L Register (PTLPE)
Figure 6-68. Slew Rate Enable for Port L Register (PTLSE)
0
0
6
6
Table 6-65. PTLPE Register Field Descriptions
Table 6-66. PTLSE Register Field Descriptions
MC9S08DZ128 Series Data Sheet, Rev. 1
PTLPE5
PTLSE5
0
0
5
5
PTLPE4
PTLSE4
NOTE
0
0
4
4
Description
Description
PTLPE3
PTLSE3
3
0
3
0
PTLPE2
PTLSE2
0
0
2
2
PTLPE1
PTLSE1
Freescale Semiconductor
0
0
1
1
PTLPE0
PTLSE0
0
0
0
0

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